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公开(公告)号:US20190245056A1
公开(公告)日:2019-08-08
申请号:US15886876
申请日:2018-02-02
申请人: International Business Machines Corporation , Centre National De La Recherche Scientifique , Ecole Centrale De Lyon
发明人: John Bruley , Eduard Albert Cartier , Catherine Dubourdieu , Martin Michael Frank , Lucie Mazet , Vijay Narayanan
IPC分类号: H01L29/51 , H01L27/088 , H01L29/66 , H01L49/02
CPC分类号: H01L29/516 , H01L27/088 , H01L28/55 , H01L29/6684
摘要: A circuit and method relating to a ferroelectric region free of extended grain boundaries through a thickness of ferroelectric film. The circuit includes an interlayer insulating film disposed on a semiconductor wafer; a first conductive film disposed on the interlayer insulating film; a ferroelectric film disposed on the first conductive film; a second conductive film disposed on the ferroelectric film; and a ferroelectric region patterned from the ferroelectric film, wherein the ferroelectric region is free of extended grain boundaries through a thickness of the ferroelectric film. The method includes depositing an interlayer insulating film over a semiconductor wafer; depositing a first conductive film over the interlayer insulating film; depositing a ferroelectric film over the first conductive film; depositing a second conductive film over the ferroelectric film; and forming a capacitor by patterning the first conductive film, the second conductive film, and the ferroelectric film.
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公开(公告)号:US20150214323A1
公开(公告)日:2015-07-30
申请号:US14681215
申请日:2015-04-08
IPC分类号: H01L29/51 , H01L27/088
CPC分类号: H01L29/516 , H01L21/823412 , H01L21/823462 , H01L27/088 , H01L29/40111 , H01L29/78 , H01L29/7843
摘要: An integrated circuit and method for forming an integrated circuit. There are at least three field-effect transistors with at least two of the field-effect transistors having the same electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. It is optional for the third field-effect transistor to have an electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. The at least three field-effect transistors are strained to varying amounts so that each of the three field-effect transistors has a threshold voltage, Vt, which is different from the Vt of the two other field-effect transistors.
摘要翻译: 一种用于形成集成电路的集成电路和方法。 存在至少三个场效应晶体管,其中至少两个场效应晶体管具有相同的电绝缘材料,其在未应变时为铁电体,或者当诱发应变时能够为铁电体。 对于第三场效应晶体管来说,具有电绝缘材料是可选的,其在未应变时为铁电体,或者当诱发应变时能够是铁电体。 至少三个场效应晶体管被应变到不同的量,使得三个场效应晶体管中的每一个具有不同于另外两个场效应晶体管的Vt的阈值电压Vt。
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公开(公告)号:US20230210027A1
公开(公告)日:2023-06-29
申请号:US18117755
申请日:2023-03-06
CPC分类号: H10N70/253 , H10N70/021 , H10N70/245 , H10N70/8416 , H10N70/8833
摘要: A method of fabricating a synaptic device is provided. The method includes forming a channel layer between a first terminal and a second terminal. The channel layer varies in resistance based on a magnesium concentration in the channel layer. The method further includes forming an electrolyte layer. The electrolyte layer includes a magnesium ion conductive material. A third terminal is formed over the electrolyte layer and applies a signal to the electrolyte layer and the channel layer.
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公开(公告)号:US20220328302A1
公开(公告)日:2022-10-13
申请号:US17851100
申请日:2022-06-28
发明人: Martin Michael Frank , John Rozen , Yohei Ogawa
IPC分类号: H01L21/02 , H01L29/788 , H01L29/78 , H01L45/00
摘要: Embodiments of the present invention are directed to forming a ternary compound using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor includes a first metal and a first ligand. The second precursor includes a second metal and a second ligand. The second ligand is selected based on the first ligand to target a second metal uptake. A substrate is exposed to the first precursor during a first pulse of an ALD cycle and the substrate is exposed to the second precursor during a second pulse of the ALD cycle, the second pulse occurring after the first pulse. The substrate is exposed to a third precursor (e.g., an oxidant) during a third pulse of the ALD cycle. The ternary compound can include a ternary oxide film.
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公开(公告)号:US12114581B2
公开(公告)日:2024-10-08
申请号:US18117755
申请日:2023-03-06
CPC分类号: H10N70/253 , H10N70/021 , H10N70/245 , H10N70/8416 , H10N70/8833
摘要: A method of fabricating a synaptic device is provided. The method includes forming a channel layer between a first terminal and a second terminal. The channel layer varies in resistance based on a magnesium concentration in the channel layer. The method further includes forming an electrolyte layer. The electrolyte layer includes a magnesium ion conductive material. A third terminal is formed over the electrolyte layer and applies a signal to the electrolyte layer and the channel layer.
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公开(公告)号:US20240202275A1
公开(公告)日:2024-06-20
申请号:US18085011
申请日:2022-12-20
CPC分类号: G06F12/0207 , G06F17/16
摘要: A system, method and computer program product for assigning deep neural network (DNN) weight matrices to a Compute-in-Memory (CiM) accelerator system, and particularly, efficient allocation strategies for assigning DNN model weight-layers to two-dimensional (2D) tiers of three-dimensional (3D) crossbar array tiles. Such efficient allocation strategies for assigning DNN model weight-layers to tiers and tiles of a CiM accelerator are optimized to minimize contention, latency and dead-time, and to maximize accelerator throughput. In one scenario, efficient allocation strategies include assigning DNN weight matrices to the 2D tiers of a 3D crossbar array tile to maximize throughput and minimize completion latency for a finite-batch-size example of an incoming workflow. In a further scenario, efficient allocation strategies assign DNN weight matrices to the 2D tiers of a 3D crossbar array tile to minimize dead-time-latency-before-next-batch-member-can-be-input in an infinite-batch-size or a continuous workflow scenario.
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公开(公告)号:US11462398B2
公开(公告)日:2022-10-04
申请号:US16514351
申请日:2019-07-17
发明人: Martin Michael Frank , John Rozen , Yohei Ogawa
IPC分类号: H01L21/02 , H01L29/788 , H01L29/78 , H01L45/00
摘要: Embodiments of the present invention are directed to forming a ternary compound using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor includes a first metal and a first ligand. The second precursor includes a second metal and a second ligand. The second ligand is selected based on the first ligand to target a second metal uptake. A substrate is exposed to the first precursor during a first pulse of an ALD cycle and the substrate is exposed to the second precursor during a second pulse of the ALD cycle, the second pulse occurring after the first pulse. The substrate is exposed to a third precursor (e.g., an oxidant) during a third pulse of the ALD cycle. The ternary compound can include a ternary oxide film.
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公开(公告)号:US20210020427A1
公开(公告)日:2021-01-21
申请号:US16516423
申请日:2019-07-19
发明人: John Rozen , Martin Michael Frank , Yohei Ogawa
IPC分类号: H01L21/02 , H01L21/28 , H01L45/00 , C23C16/40 , C23C16/455
摘要: Embodiments of the present invention are directed to forming a sub-stoichiometric metal-oxide film using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor can include a metal and a first ligand. The second precursor can include the same metal and a second ligand. A substrate can be exposed to the first precursor during a first pulse of an ALD cycle. The substrate can be exposed to the second precursor during a second pulse of the ALD cycle. The second pulse can occur directly after the first pulse without an intervening thermal oxidant. The substrate can be exposed to the thermal oxidant during a third pulse of the ALD cycle.
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公开(公告)号:US20240185057A1
公开(公告)日:2024-06-06
申请号:US18074567
申请日:2022-12-05
CPC分类号: G06N3/08 , G06F3/0625 , G06F3/0638 , G06F3/0679 , G06N3/065
摘要: Systems, methods, and semiconductor devices for transfer learning are described. A semiconductor device can include a first non-volatile memory (NVM) and a second NVM. The first NVM can be configured to store weights of a first set of layers of a machine learning model. The weights of the first set of layers can be fixed. The second NVM can be configured to store weights of a second set of layers of the machine learning model. The weights of the second set of layers can be adjustable.
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公开(公告)号:US11889771B2
公开(公告)日:2024-01-30
申请号:US17136107
申请日:2020-12-29
发明人: Cheng-Wei Cheng , Huai-Yu Cheng , I-Ting Kuo , Robert L. Bruce , Martin Michael Frank , Hiroyuki Miyazoe
CPC分类号: H10N70/041 , H10B63/24 , H10N70/231 , H10N70/826 , H10N70/8413 , H10N70/8825 , H10N70/8828
摘要: A method for mitigating moisture driven degradation of silicon doped chalcogenides includes placing a silicon doped chalcogenide composition in a process chamber, passivating dangling silicon bonds of the silicon doped chalcogenide composition by flooding the process chamber with forming gas or with hydrogen plasma, purging the forming gas or the hydrogen plasma from the process chamber, and removing the passivated silicon doped chalcogenide composition from the process chamber.
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