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    Apparatus for improving performance of field programmable gate arrays and associated methods
    1.
    发明授权
    Apparatus for improving performance of field programmable gate arrays and associated methods 有权
    用于提高现场可编程门阵列性能的装置及相关方法

    公开(公告)号：US08698516B2

    公开(公告)日：2014-04-15

    申请号：US13214144

    申请日：2011-08-19

    申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

    发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

    IPC分类号： H03K17/16

    CPC分类号： H03K19/17784 ,  H03K19/17792

    摘要： A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.

    摘要翻译： 现场可编程门阵列（FPGA）包括一组监视器电路，其适于为FPGA中的至少一个电路提供过程，电压和温度的指示，以及控制器，其适于导出所述at的至少一个电路的体偏值的范围 用于至少一个电路的过程，电压和温度的指示的至少一个电路。 FPGA还包括体偏置发生器，其适于向至少一个电路中的至少一个晶体管提供体偏置信号。 体偏置信号具有在体偏值范围内的值。

    APPARATUS FOR IMPROVING PERFORMANCE OF FIELD PROGRAMMABLE GATE ARRAYS AND ASSOCIATED METHODS
    2.
    发明申请
    APPARATUS FOR IMPROVING PERFORMANCE OF FIELD PROGRAMMABLE GATE ARRAYS AND ASSOCIATED METHODS 有权
    改进现场可编程门阵列性能的方法及相关方法

    公开(公告)号：US20130043902A1

    公开(公告)日：2013-02-21

    申请号：US13214144

    申请日：2011-08-19

    申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

    发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17784 ,  H03K19/17792

    摘要： A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.

    摘要翻译： 现场可编程门阵列（FPGA）包括一组监视器电路，其适于为FPGA中的至少一个电路提供过程，电压和温度的指示，以及控制器，其适于导出针对 用于至少一个电路的过程，电压和温度的指示的至少一个电路。 FPGA还包括体偏置发生器，其适于向至少一个电路中的至少一个晶体管提供体偏置信号。 体偏置信号具有在体偏值范围内的值。

    Memory elements with voltage overstress protection
    3.
    发明授权
    Memory elements with voltage overstress protection 有权
    具有电压过载保护功能的存储器元件

    公开(公告)号：US08369175B1

    公开(公告)日：2013-02-05

    申请号：US12874152

    申请日：2010-09-01

    申请人： Lin-Shih Liu ,  Andy L. Lee ,  Ping-Chen Liu ,  Irfan Rahim ,  Srinivas Perisetty

    发明人： Lin-Shih Liu ,  Andy L. Lee ,  Ping-Chen Liu ,  Irfan Rahim ,  Srinivas Perisetty

    IPC分类号： G11C5/14

    CPC分类号： G11C11/412 ,  G11C15/04

    摘要： Integrated circuits may include memory elements that are provided with voltage overstress protection. One suitable arrangement of a memory cell may include a latch with two cross-coupled inverters. Each of the two cross-coupled inverters may be coupled between first and second power supply lines and may include a transistor with a gate that is connected to a separate power supply line. Another suitable memory cell arrangement may include three cross-coupled circuits. Two of the three circuits may be powered by a first positive power supply line, while the remaining circuit may be powered by a second positive power supply line. These memory cells may be used to provide an elevated positive static control signal and a lowered ground static control signal to a corresponding pass gate. These memory cells may include access transistors and read buffer circuits that are used during read/write operations.

    摘要翻译： 集成电路可以包括具有电压过应力保护的存储器元件。 存储单元的一种合适布置可以包括具有两个交叉耦合的反相器的锁存器。 两个交叉耦合反相器中的每一个可以耦合在第一和第二电源线之间，并且可以包括具有连接到单独的电源线的栅极的晶体管。 另一种合适的存储单元布置可以包括三个交叉耦合电路。 三个电路中的两个可以由第一正电源线供电，而剩余电路可以由第二正电源线供电。 这些存储单元可用于向对应的通道提供升高的正静态控制信号和降低的地面静态控制信号。 这些存储单元可以包括在读/写操作期间使用的存取晶体管和读缓冲电路。

    Low voltage supply comparator and a method to operate the comparator
    4.
    发明授权
    Low voltage supply comparator and a method to operate the comparator 有权
    低电压电源比较器和一种操作比较器的方法

    公开(公告)号：US08575977B1

    公开(公告)日：2013-11-05

    申请号：US13428912

    申请日：2012-03-23

    申请人： Justin Jon Philpott ,  Arvind Sherigar ,  Jeffery Chow ,  Ping-Chen Liu

    发明人： Justin Jon Philpott ,  Arvind Sherigar ,  Jeffery Chow ,  Ping-Chen Liu

    IPC分类号： H03L7/00

    CPC分类号： H03K5/2481

    摘要： A comparator is disclosed. The comparator includes a mirror circuit that is electrically coupled to a first voltage source and a second voltage source. The first voltage source produces a first voltage and the second voltage source produces a second voltage. The comparator also includes a first positive metal oxide semiconductor (PMOS) transistor electrically coupled to the first voltage source and an output terminal. The first PMOS transistor is biased by the mirror circuit. The comparator also includes a first negative metal oxide semiconductor (NMOS) that is electrically coupled to a ground terminal and the output terminal. The first NMOS transistor is also biased by the mirror circuit. An electrical current flowing across the first NMOS transistor is mirrored from an electrical current flowing through the first PMOS transistor. A method to operate the comparator and a comparator system is also disclosed.

    摘要翻译： 公开了一种比较器。 比较器包括电耦合到第一电压源和第二电压源的镜电路。 第一电压源产生第一电压，第二电压源产生第二电压。 比较器还包括电耦合到第一电压源的第一正金属氧化物半导体（PMOS）晶体管和输出端子。 第一个PMOS晶体管被镜像电路偏置。 比较器还包括电耦合到接地端子和输出端子的第一负金属氧化物半导体（NMOS）。 第一个NMOS晶体管也被镜像电路偏置。 流经第一NMOS晶体管的电流与流过第一PMOS晶体管的电流相反。 还公开了一种操作比较器和比较器系统的方法。

    Clock signal-distribution network for an integrated circuit
    6.
    发明授权
    Clock signal-distribution network for an integrated circuit 有权
    用于集成电路的时钟信号分配网络

    公开(公告)号：US07145362B1

    公开(公告)日：2006-12-05

    申请号：US10981973

    申请日：2004-11-05

    申请人： Jason R. Bergendahl ,  Ping-Chen Liu

    发明人： Jason R. Bergendahl ,  Ping-Chen Liu

    IPC分类号： H03K19/00

    CPC分类号： H03K5/15013 ,  G06F1/10

    摘要： Apparatus for signal distribution, and more particularly to a clock-distribution network in an integrated circuit, is described. A programmable logic device 300 includes an input buffer (814, 824) and an input signal distribution buffer (369) coupled to the input buffer (814, 824). The input signal distribution buffer (369) is configured to distribute a clock signal (902) within an input/output block clock region (304A, 304B). Signal lines (371UD) extend to at least one other input signal distribution buffer (369).

    摘要翻译： 描述了用于信号分配的装置，更具体地涉及集成电路中的时钟分配网络。 可编程逻辑器件300包括输入缓冲器（814,824）和耦合到输入缓冲器（814,824）的输入信号分配缓冲器（369）。 输入信号分配缓冲器（369）被配置为在时钟信号（902）内分配输入/输出块时钟区域（304A，304B）。 信号线（371 UD）延伸到至少一个其它输入信号分配缓冲器（369）。

    Voltage regulator circuitry with adaptive compensation
    7.
    发明授权
    Voltage regulator circuitry with adaptive compensation 有权
    具有自适应补偿的稳压电路

    公开(公告)号：US08493043B2

    公开(公告)日：2013-07-23

    申请号：US12766622

    申请日：2010-04-23

    申请人： Thien Le ,  Ping-Chen Liu

    发明人： Thien Le ,  Ping-Chen Liu

    IPC分类号： G05F1/00

    CPC分类号： G05F1/575

    摘要： Voltage regulator circuitry is provided. The voltage regulator circuitry may contain a drive transistor that is controlled by the output of an operational amplifier. The drive transistor may supply a regulated voltage to a load. The operational amplifier may compare a reference voltage and a feedback signal at its inputs. The operational amplifier may include first and second stages. An adjustable resistor may be provided between the first and second stages. Control circuitry may control the resistance of the adjustable resistor based on the amount of current flowing through the load to ensure stable operation of the voltage regulator circuitry. Overshoot and undershoot detection and compensation circuitry may compensate for overshoot and undershoot in the regulated voltage. Voltage ramp control circuitry may be used to control the ramp rate of the regulated voltage.

    摘要翻译： 提供稳压电路。 电压调节器电路可以包含由运算放大器的输出控制的驱动晶体管。 驱动晶体管可以向负载提供调节电压。 运算放大器可以在其输入端比较参考电压和反馈信号。 运算放大器可以包括第一和第二级。 可以在第一和第二级之间设置可调电阻器。 控制电路可以基于流过负载的电流量来控制可调电阻器的电阻，以确保稳压器电路的稳定运行。 过冲和下冲检测和补偿电路可能会补偿调节电压中的过冲和下冲。 电压斜坡控制电路可用于控制调节电压的斜坡率。

    Power regulator circuitry for programmable logic device memory elements
    8.
    发明申请
    Power regulator circuitry for programmable logic device memory elements 有权
    用于可编程逻辑器件存储器元件的功率调节器电路

    公开(公告)号：US20080265855A1

    公开(公告)日：2008-10-30

    申请号：US11799228

    申请日：2007-04-30

    申请人： William Bradley Vest ,  Ping-Chen Liu ,  Thien Le

    发明人： William Bradley Vest ,  Ping-Chen Liu ,  Thien Le

    IPC分类号： G05F1/00

    CPC分类号： H03K19/0013 ,  G11C5/147 ,  H03K19/1776 ,  H03K19/17792

    摘要： Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address drivers may be used to supply address signals to the address transistors. The power regulator circuitry may include an address power supply circuit that produces a time-varying address power supply voltage to the address drivers and storage element power supply circuits that provide time-varying storage element power supply voltages to the cross-coupled inverters in the storage elements. Unity gain buffers may be used to distribute a reference voltage from a bandgap voltage reference to the power supply circuits. The power supply circuits may use voltage dividers and p-channel metal-oxide-semiconductor control transistors.

    摘要翻译： 提供了可编程逻辑器件集成电路上可编程存储器元件的功率调节器电路。 可编程存储器元件可各自包括由交叉耦合的反相器和地址晶体管形成的存储元件。 地址驱动器可用于向地址晶体管提供地址信号。 功率调节器电路可以包括地址电源电路，其向地址驱动器和存储元件电源电路产生时变地址电源电压，所述地址驱动器和存储元件电源电路向存储器中的交叉耦合的反相器提供时变存储元件电源电压 元素。 单位增益缓冲器可以用于将带隙电压基准的参考电压分配给电源电路。 电源电路可以使用分压器和p沟道金属氧化物半导体控制晶体管。

    Merged charge pump
    10.
    发明授权
    Merged charge pump 有权
    合并电荷泵

    公开(公告)号：US06980045B1

    公开(公告)日：2005-12-27

    申请号：US10729658

    申请日：2003-12-05

    申请人： Ping-Chen Liu

    发明人： Ping-Chen Liu

    IPC分类号： G05F3/08 ,  H02M3/07

    CPC分类号： H02M3/073 ,  H02M2003/075 ,  H02M2003/076

    摘要： A charge pump circuit for generating various pumped voltages includes a first charge pump including a plurality of first charge pump stages responsive to a first set of clock signals and having threshold voltage cancellation circuitry, a second charge pump including a plurality of second charge pump stages responsive to a second set of clock signals different from the first clock signals, and a switching circuit configured to selectively connect the second charge pump in series between the first charge pump and a voltage rail in response to a mode signal (MODE). For some embodiments, a plurality of the charge pump circuits can be selectively connected in parallel in response to corresponding select signals to generate various drive currents.

    摘要翻译： 用于产生各种泵浦电压的电荷泵电路包括第一电荷泵，其包括响应于第一组时钟信号并具有阈值电压消除电路的多个第一电荷泵级，第二电荷泵，包括多个第二电荷泵级， 到与第一时钟信号不同的第二组时钟信号，以及开关电路，被配置为响应于模式信号（MODE）而将第二电荷泵串联选择性地连接在第一电荷泵和电压轨之间。 对于一些实施例，响应于相应的选择信号，多个电荷泵电路可以并联选择性地并联以产生各种驱动电流。