公开(公告)号：US4492974A

公开(公告)日：1985-01-08

申请号：US350589

申请日：1982-02-22

申请人： Isao Yoshida ,  Takeaki Okabe ,  Mineo Katsueda ,  Minoru Nagata ,  Toshiaki Masuhara ,  Kazutoshi Ashikawa ,  Hideaki Kato ,  Mitsuo Ito ,  Shigeo Ohtaka ,  Osamu Minato ,  Yoshio Sakai

发明人： Isao Yoshida ,  Takeaki Okabe ,  Mineo Katsueda ,  Minoru Nagata ,  Toshiaki Masuhara ,  Kazutoshi Ashikawa ,  Hideaki Kato ,  Mitsuo Ito ,  Shigeo Ohtaka ,  Osamu Minato ,  Yoshio Sakai

IPC分类号： H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/78 ,  H01L29/861 ,  H01L29/90 ,  H02H3/20

CPC分类号： H01L29/7811 ,  H01L27/0255 ,  H01L27/0688 ,  H01L29/7808 ,  H01L29/861 ,  H01L2924/0002

摘要： A semiconductor integrated circuit device is provided to include a vertical type MOSFET and a gate protection element for the MOSFET. The vertical type MOSFET is made up of a silicon layer of n-type conductivity formed on an n.sup.+ -type silicon substrate, a base region of p-type conductivity formed in the surface of the silicon layer of n-type conductivity, an n.sup.+ -type source region provided in the base region, and a gate electrode formed on a portion of the base region through a gate insulating film. The silicon substrate serves as the drain. The gate protection element is formed of a polycrystalline silicon layer which is provided on the base region through an insulating film and includes at least one pn junction. By virtue of forming the gate protection element over the base region rather than directly over the substrate, a more stable operation is achieved.

摘要翻译： 提供半导体集成电路器件以包括用于MOSFET的垂直型MOSFET和栅极保护元件。 垂直型MOSFET由n +型硅衬底上形成的n型导电硅层，n型导电性硅层表面形成的p型导电基极区，n +型硅衬底， 设置在基极区域中的源极区，以及通过栅极绝缘膜形成在基极区域的一部分上的栅电极。 硅衬底用作漏极。 栅极保护元件由多晶硅层形成，该多晶硅层通过绝缘膜设置在基极区上并且包括至少一个pn结。 通过在基极区域而不是直接在衬底上形成栅极保护元件，实现更稳定的操作。

公开(公告)号：US4814288A

公开(公告)日：1989-03-21

申请号：US72164

申请日：1987-07-10

申请人： Masatoshi Kimura ,  Takeaki Okabe ,  Isao Yoshida ,  Kouzou Sakamoto ,  Kazuo Hoya ,  Kouichiro Satonaka ,  Toyomasa Koda ,  Shigeo Ohtaka

发明人： Masatoshi Kimura ,  Takeaki Okabe ,  Isao Yoshida ,  Kouzou Sakamoto ,  Kazuo Hoya ,  Kouichiro Satonaka ,  Toyomasa Koda ,  Shigeo Ohtaka

IPC分类号： H01L27/08 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L21/20 ,  H01L21/302

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： A method of fabricating semiconductor devices which include vertical elements and control elements. A well is formed by etching in a semiconductor substrate of a first conductivity type, and a first epitaxial layer having a second conductivity type opposite to the first conductivity type is epitaxially grown, followed by etching and/or grinding and/or polishing to fill said well. Further, a second epitaxial layer of the first conductivity type is epitaxially grown on the substrate and on the first epitaxial layer, and an impurity-doped layer of the second conductivity type for isolation is formed in the second epitaxial layer to penetrate therethrough. A first element is formed in the second epitaxial layer in a portion that corresponds to the well, and a second element having a vertical structure and having a current capability higher than that of the first element is formed except a portion of the second epitaxial layer that corresponds to the well.

摘要翻译： 一种制造包括垂直元件和控制元件的半导体器件的方法。 通过在第一导电类型的半导体衬底中蚀刻形成阱，并且外延生长具有与第一导电类型相反的第二导电类型的第一外延层，随后进行蚀刻和/或研磨和/或抛光以填充所述 好。 此外，第一导电类型的第二外延层在衬底和第一外延层上外延生长，并且在第二外延层中形成用于隔离的第二导电类型的杂质掺杂层以穿透其中。 在对应于阱的部分中的第二外延层中形成第一元件，并且除了第二外延层的一部分之外，形成具有比第一元件的电流能力高的垂直结构并具有电流能力的第二元件， 对应于井。

公开(公告)号：US5638246A

公开(公告)日：1997-06-10

申请号：US10572

申请日：1993-01-28

申请人： Kozo Sakamoto ,  Isao Yoshida ,  Masatoshi Morikawa ,  Shigeo Ohtaka ,  Hideki Tsunoda

发明人： Kozo Sakamoto ,  Isao Yoshida ,  Masatoshi Morikawa ,  Shigeo Ohtaka ,  Hideki Tsunoda

IPC分类号： H02H5/04 ,  H03K17/08 ,  H03K17/082

CPC分类号： H02H5/044 ,  H03K17/0822 ,  H03K2017/0806

摘要： In a semiconductor device including a power MOSFET (M.sub.0) for the output stage, a temperature detection circuit produces an output signal upon detecting an abnormal rise in the chip temperature, the signal turns on a set input element (M.sub.1) in a latch circuit so that the latch circuit becomes a set state, the set output of the latch circuit turns on a control element (M.sub.5), causing the power MOSFET to become non-conductive so that it is protected from destruction. The latch circuit is not brought to a reset state even if the external gate terminal of the device is brought to zero volt. With a voltage outside the range of the normal input signal, e.g., a large negative voltage, being applied to the external gate terminal, the gate capacitance of the control element (M.sub.5) discharges, and consequently the latch circuit is brought to the reset state and the protective operation is cancelled. The semiconductor device is further provided with an external reset terminal, and the protective operation can also be cancelled through the application of a reset signal to the external reset terminal. The semiconductor device is protected from destruction and also from deterioration of characteristics of the power MOSFET (M.sub.0), and yet the protective operation is not cancelled erroneously by the normal input signal.

摘要翻译： 在包括用于输出级的功率MOSFET（M0）的半导体器件中，温度检测电路在检测到芯片温度的异常升高时产生输出信号，该信号使锁存电路中的设定输入元件（M1）接通，从而 锁存电路变为置位状态，锁存电路的设定输出导通控制元件（M5），使功率MOSFET变得不导通，从而防止其破坏。 即使器件的外部栅极端子达到零伏，锁存电路也不会进入复位状态。 在外部栅极端子施加正常输入信号（例如，大的负电压）的范围之外的电压时，控制元件（M5）的栅极电容放电，因此锁存电路进入复位状态 并且保护操作被取消。 半导体器件还具有外部复位端子，并且还可以通过向外部复位端子施加复位信号来取消保护操作。 保护半导体器件不受破坏，也可以防止功率MOSFET（M0）的特性恶化，而保护操作也不会被正常输入信号错误地消除。

公开(公告)号：US5196354A

公开(公告)日：1993-03-23

申请号：US582583

申请日：1990-09-14

申请人： Shigeo Ohtaka ,  Akio Andoo ,  Tetsuo Iijima

发明人： Shigeo Ohtaka ,  Akio Andoo ,  Tetsuo Iijima

IPC分类号： H01L21/312 ,  H01L21/263 ,  H01L21/336 ,  H01L23/29 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/408 ,  H01L21/2633 ,  H01L23/293 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/13091 ,  Y10S438/904 ,  Y10S438/958

摘要： A semiconductor device has a semiconductor substrate, an insulated gate field-effect transistor section formed in the substrate and a peripheral section formed in the substrate and arranged to substantially surround the field-effect transistor section. A passivation layer of an organic material is provided over that part of the substrate in which the field-effect transistor section is not located. The device may be resin mold packaged for an enhanced humidity-resistance by making use of the fact tht the peripheral portion of the device is covered with organic resin.

摘要翻译： 半导体器件具有半导体衬底，形成在衬底中的绝缘栅场效应晶体管部分和形成在衬底中并围绕场效应晶体管部分布置的外围部分。 在场效应晶体管部分不位于衬底的该部分上提供有机材料的钝化层。 该装置可以通过利用装置的周边部分被有机树脂覆盖的事实来树脂模制包装以增强耐湿性。