摘要:
Parallel signal processor (10) (FIG. 2) performs a Fourier Transformation of an input signal; The transformation coefficients are converted once to logarithmic form and stored in a cache memory. The input data is converted serially to logarithmic form, and fed to all processing units in parallel. The processing units compute their respective products as additions in the logarithmic domain. Then, the products are converted back to the normal domain. The products with the correct sign are summed by an accumulator of the respective processing element. After the last signal data point has run through the processing elements and the last products are added to their respective sums, all complex output signal data points are complete simultaneously.
摘要:
With reference to FIG. 1 signal processor (10) for performing transformations of sets of input data points comprises a memory for storing a first half input data points and a second half input data points, an adder unit for pairwise adding one real part of each one first half input data point and a second half input data point and providing adder output data, and a computing unit for performing transformations upon the adder output data. Addition for data reduction and data transformation are carried out simultaneously by different units.
摘要:
The invention relates to a method for electronically representing a number V in a binary data word. Both the exponent and the mantissa are represented as 2' complement. The mantissa is normalized to 0.1.F if the number V is positive where F is the fraction of the mantissa. In case that the number V is negative the fraction F is normalized to 10.F. Usage of this format allows to design an improved adder which requires less hardware.
摘要:
A multiply-multiply-accumulate (MMA) system (10) efficiently evaluates matrix products X=F*C. Matrix C is dissected into submatrices A and B taking advantage of symmetry in C. LOG unit (14) converts B, A, and F to LOG values B', A' and F'. These are summed in K parallel calculating units CU's (18) and converted back to Normal domain as P=F*B*A in ALOG units (22) and sent to accumulators ACU's (24). The ACU's (24) accumulate the results. An output buffer (26) combines the results. The B', A' values (32,34) are held in a cache memory (20) and the LOG sums are performed in two steps with intermediate storage.
摘要翻译:乘法 - 累积(MMA)系统(10)有效地评估矩阵乘积X = F * C。 利用C中的对称性将矩阵C解剖为子矩阵A和B. LOG单元(14)将B,A和F转换为LOG值B',A'和F'。 这些以K并行计算单元CU(18)相加,并在ALOG单元(22)中被转换回正常域为P = F * B * A并发送到累加器ACU(24)。 ACU(24)积累了结果。 输出缓冲器(26)组合结果。 B',A'值(32,34)被保存在高速缓冲存储器(20)中,并且LOG和数以两个步骤执行中间存储。
摘要:
Preferred embodiments of a method and an apparatus for controlling power during a dispatch group call in a wireless communication system are described. A base station (142) monitors for a transmission from a plurality of mobile stations (270) via a first communication resource during a time period. The base station (142) adjusts transmission power associated with a second communication resource based on the transmission from the plurality of mobile stations (270) via the first communication resource. Further, the base station (142) determines whether the transmission power associated with the second communication resource is above a transmission power threshold. In response to a failure to receive the transmission from the plurality of mobile stations (270) via the first communication resource during the time period and a failure to detect the transmission power associated with the second communication resource being above the power threshold, the base station (142) terminates transmissions to the plurality of mobile stations (270) via the second communication resource.
摘要:
A video signal is converted into a coefficient signal for each frame in a video image. Each coefficient signal comprises block coefficient signals which represent the pixels in a pixel map block (420) in a pixel map (410) with the coefficients in a hybrid polynomial. The coefficient signal for only selected frames is transmitted to a receiving computer (130). The coefficient signals are selected based on a number of coefficients in the coefficient signal for a current frame that vary from corresponding coefficients in the coefficient signal for a sequentially previous frame.
摘要:
A computer processor that performs operations in a logarithmic number system (LNS) domain includes a log converter (20) which generates log signals, a data pipeline (22), a plurality of processing elements (231a-f) coupled to respective stages (24a-d) of the data pipeline, an inverse-log converter (28), and a programmable accumulator (232) that performs various summing operations to produce an output signal. An instruction, selected from a set of instructions, is decoded by a control unit (234) to configure the computer processor to perform operations on one or more data streams. Mathematical operations that can be performed by the processor include matrix multiplication, matrix-inversion, fast Fourier transforms (FFT), auto-correlation, cross-correlation, discrete cosine transforms (DCT), polynomial equations, and difference equations in general, such as those used to approximate infinite impulse response (IIR) and finite impulse response (FIR) filters. The computer processor can be used as a co-processor (340) in a general purpose computer system.
摘要:
A method and system for an L.sub.2 norm operation are provided. A sequence of input signals is converted to a sequence of log signals. The sequence of log signals is distributed through a data pipeline to a plurality of processing elements which effectively multiply each log signal by a factor of two to produce a plurality of term signals. The term signals are then converted to inverse-log signals which are summed to produce a feedback signal. The square-root of the feedback signal is computed to generate an output signal. The log/inverse-log conversions of signals are based on estimating a log/inverse-log function using a second-order polynomial. The L.sub.2 norm operation can be performed using the distance between two vectors.
摘要:
A pixel map signal is converted into a coefficient signal of block coefficient signals, each representing the pixels in a pixel map block (420) in a pixel map (410) with the coefficients in a hybrid polynomial. The coefficient signal is quantized by dividing each of the coefficient values in each of the block coefficient signals by quantization factors to produce quantized coefficient values which replace the coefficient values. Block coefficient signals which represent an edge block (424) in the pixel map (410) are divided by larger quantization factors than block coefficient signals which represent a center block (422) in the pixel map (410). As a result, smaller quantized coefficient values are obtained so that block coefficient signals which represent an edge block (424) are compressed to a greater extent than block coefficient signals that represent a center block (422) in the pixel map (410).
摘要:
A method and system for an FIR filter are provided. A sequence of input signal is converted to a corresponding sequence of log signals. FIR filtering coefficients are then added to each log signal to generate a plurality of term signals. The term signals are then converted to inverse-log signals, and the inverse-log signals are summed to produce an output signal. Log/inverse-log conversions of signals are based on estimating a log/inverse-log function using a second-order polynomial.