公开(公告)号：US06329276B1

公开(公告)日：2001-12-11

申请号：US09392470

申请日：1999-09-09

申请人： Ja-Hum Ku ,  Soo-Geun Lee ,  Chul-Sung Kim ,  Tae-Wook Seo ,  Eung-Joon Lee ,  Joo-Hyuk Chung

发明人： Ja-Hum Ku ,  Soo-Geun Lee ,  Chul-Sung Kim ,  Tae-Wook Seo ,  Eung-Joon Lee ,  Joo-Hyuk Chung

IPC分类号： H01L213205

CPC分类号： H01L29/665 ,  H01L21/28518

摘要： There is provided a semiconductor device fabrication method. In the method, a gate layer is formed on a semiconductor substrate and patterned to form a first resultant structure, a metal layer is formed on the first resultant structure, a capping layer is formed on the metal layer, a metal silicide is formed on the gate layer by heating the substrate at a first temperature, unreacted metal layer and first capping layer are removed to form a second resultant structure, a second capping layer is formed on the second resultant structure, and the substrate is heated at a second temperature higher than the first temperature. The second capping layer suppresses a silicidation rate in the secondary heat treatment, thereby allowing a silicide of a good morphology to be achieved.

摘要翻译： 提供了半导体器件制造方法。 在该方法中，在半导体衬底上形成栅极层并形成第一结构，在第一结果结构上形成金属层，在金属层上形成覆盖层，在金属层上形成金属硅化物 通过在第一温度下加热衬底，去除未反应的金属层和第一覆盖层以形成第二结构结构，在第二结构结构上形成第二覆盖层，并且将衬底在高于 第一个温度。 第二覆盖层抑制二次热处理中的硅化率，从而实现良好形态的硅化物。

公开(公告)号：US06624496B2

公开(公告)日：2003-09-23

申请号：US10044991

申请日：2002-01-15

申请人： Ja-Hum Ku ,  Dong-Ho Ahn ,  Chul-Sung Kim ,  Jae-Yoon Yoo ,  Sug-Hun Hong ,  Chul-Joon Choi

发明人： Ja-Hum Ku ,  Dong-Ho Ahn ,  Chul-Sung Kim ,  Jae-Yoon Yoo ,  Sug-Hun Hong ,  Chul-Joon Choi

IPC分类号： H01L2176

CPC分类号： H01L29/66598 ,  H01L21/28518 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66636

摘要： A method of forming a T-shaped isolation layer, a method of forming an elevated salicide source/drain region using the same, and a semiconductor device having the T-shaped isolation layer are provided. In the method of forming the T-shaped isolation layer, an isolation layer having a narrow trench region in the lower portion thereof and a wide trench region in the upper portion thereof is formed on a semiconductor substrate. Also, in the method of forming the elevated salicide source/drain region, the method of forming the T-shaped isolation layer is used. In particular, conductive impurities can also be implanted into the lower portion of the wide trench region which constitutes the head of the T-shaped isolation layer and is extended to both sides from the upper end of the narrow trench region by controlling the depth of the wide trench region in an ion implantation step for forming the source/drain region.

公开(公告)号：US07514354B2

公开(公告)日：2009-04-07

申请号：US11323328

申请日：2005-12-30

申请人： Ki-Chul Park ,  Ja-Hum Ku ,  Seung-Man Choi

发明人： Ki-Chul Park ,  Ja-Hum Ku ,  Seung-Man Choi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor substrate and etching the dielectric material to form a dual damascene recess structure including a via hole and trench. A layer of first conductive material is then conformally deposited to fill the via hole with the first conductive material, and the layer of first conductive material is etched to remove the first conductive material from the trench and an upper region of the via hole below the trench. A layer of second conductive material is then deposited to fill the trench and upper region of the via hole with the second conductive material.

摘要翻译： 提供了用于形成使用不同导体材料填充通孔和线沟槽的双镶嵌互连结构的方法。 例如，形成互连结构的方法包括在半导体衬底上沉积介电材料并蚀刻电介质材料以形成包括通孔和沟槽的双镶嵌凹部结构。 然后共形沉积第一导电材料层以用第一导电材料填充通孔，并且蚀刻第一导电材料层以从沟槽移除第一导电材料，并且在沟槽下方的通孔的上部区域 。 然后沉积第二导电材料层，以用第二导电材料填充通孔的沟槽和上部区域。

公开(公告)号：US07232756B2

公开(公告)日：2007-06-19

申请号：US10812003

申请日：2004-03-30

申请人： Ja-Hum Ku ,  Kwan-Jong Roh ,  Min-Chul Sun ,  Min-Joo Kim ,  Sug-Woo Jung ,  Sun-Pil Youn

发明人： Ja-Hum Ku ,  Kwan-Jong Roh ,  Min-Chul Sun ,  Min-Joo Kim ,  Sug-Woo Jung ,  Sun-Pil Youn

IPC分类号： H01L21/44

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Provided are exemplary methods for forming a semiconductor devices incorporating silicide layers formed at temperatures below about 700° C., such as nickel silicides, that are formed after completion of a silicide blocking layer (SBL). The formation of the SBL tends to deactivate dopant species in the gate, lightly-doped drain and/or source/drain regions. The exemplary methods include a post-SBL activation anneal either in place of or in addition to the traditional post-implant activation anneal. The use of the post-SBL anneal produces CMOS transistors having properties that reflect reactivation of sufficient dopant to overcome the SBL process effects, while allowing the use of lower temperature silicides, including nickel silicides and, in particular, nickel silicides incorporating a minor portion of an alloying metal, such as tantalum, the exhibits reduced agglomeration and improved temperature stability.

摘要翻译： 提供了形成在硅化物阻挡层（SBL）完成之后形成的在低于约700℃的温度下形成的硅化物层的半导体器件（例如硅化镍）的示例性方法。 SBL的形成倾向于使栅极，轻掺杂漏极和/或源极/漏极区域中的掺杂物质失活。 示例性方法包括后SBL激活退火，代替传统的植入物后激活退火或替代传统的植入后激活退火。 后SBL退火的使用产生具有反映充分掺杂剂的再活化以克服SBL工艺效应的性质的CMOS晶体管，同时允许使用较低温度的硅化物，包括硅化镍，特别是掺入较小部分的硅化镍 合金金属如钽，表现出减少的团聚和改善的温度稳定性。

公开(公告)号：US20070082439A1

公开(公告)日：2007-04-12

申请号：US11246471

申请日：2005-10-07

申请人： Jae-Eon Park ,  Ja-Hum Ku ,  Jun-Jung Kim ,  Dae-Kwon Kang ,  Young Teh

发明人： Jae-Eon Park ,  Ja-Hum Ku ,  Jun-Jung Kim ,  Dae-Kwon Kang ,  Young Teh

IPC分类号： H01L21/8238 ,  H01L29/788

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/268 ,  H01L21/3185 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/7843

摘要： In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.

摘要翻译： 在具有用于改善电子迁移率的双应力衬垫的半导体器件中，双应力衬垫包括形成在PMOSFET上的第一衬垫部分和形成在NMOSFET上的第二衬垫部分。 第一衬里部分具有第一压缩应力，并且第二衬套部分具有小于第一压缩应力的第二压缩应力。 双应力衬垫可以通过在其上形成PMOSFET和NMOSFET的半导体衬底上形成应力衬垫而形成，并且选择性地暴露在NMOSFET上的应力衬垫的一部分。

公开(公告)号：US07084061B2

公开(公告)日：2006-08-01

申请号：US10799788

申请日：2004-03-12

申请人： Min-Chul Sun ,  Ja-Hum Ku ,  Sug-Woo Jung ,  Sun-Pil Youn ,  Min-Joo Kim ,  Kwan-Jong Roh

发明人： Min-Chul Sun ,  Ja-Hum Ku ,  Sug-Woo Jung ,  Sun-Pil Youn ,  Min-Joo Kim ,  Kwan-Jong Roh

IPC分类号： H01L21/44

CPC分类号： H01L29/7843 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods of fabricating a semiconductor device having a MOS transistor with a strained channel are provided. The method includes forming a MOS transistor at a portion of a semiconductor substrate. The MOS transistor is formed to have source/drain regions spaced apart from each other and a gate electrode located over a channel region between the source/drain regions. A stress layer is formed on the semiconductor substrate having the MOS transistor. The stress layer is then annealed to convert a physical stress of the stress layer into a tensile stress or increase a tensile stress of the stress layer.

摘要翻译： 提供了制造具有具有应变通道的MOS晶体管的半导体器件的方法。 该方法包括在半导体衬底的一部分处形成MOS晶体管。 MOS晶体管形成为具有彼此间隔开的源极/漏极区域和位于源极/漏极区域之间的沟道区域上方的栅极电极。 在具有MOS晶体管的半导体衬底上形成应力层。 然后应力层退火以将应力层的物理应力转变为拉伸应力或增加应力层的拉伸应力。

公开(公告)号：US07772643B2

公开(公告)日：2010-08-10

申请号：US12457323

申请日：2009-06-08

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC分类号： H01L29/94 ,  H01L29/78

CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

摘要翻译： 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是在富H2气氛中使用H 2 O和H 2的分压的湿式氧化工艺，以氧化基板和金属栅极图案的部分，同时抑制 可以包括在金属栅极图案中的金属层的氧化。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

公开(公告)号：US07576407B2

公开(公告)日：2009-08-18

申请号：US11411341

申请日：2006-04-26

申请人： Young-Gun Ko ,  Ja-Hum Ku ,  Minchul Sun ,  Robert Weiser

发明人： Young-Gun Ko ,  Ja-Hum Ku ,  Minchul Sun ,  Robert Weiser

IPC分类号： H01L29/72

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Electrically programmable integrated fuses are provided for low power applications. Integrated fuse devices have stacked structures with a polysilicon layer and a conductive layer formed on the polysilicon layer. The integrated fuses have structural features that enable the fuses to be reliably and efficiently programmed using low programming currents/voltages, while achieving consistency in fusing locations. For example, programming reliability and consistency is achieved by forming the conductive layers with varied thickness and forming the polysilicon layers with varied doping profiles, to provide more precise localized regions in which fusing events readily occur.

摘要翻译： 为低功率应用提供电可编程集成保险丝。 集成保险丝装置具有多晶硅层和形成在多晶硅层上的导电层的堆叠结构。 集成保险丝具有结构特征，可以使熔断器在低编程电流/电压下可靠且高效地编程，同时实现熔断位置的一致性。 例如，通过形成具有不同厚度的导电层并且形成具有变化的掺杂分布的多晶硅层来实现编程的可靠性和一致性，以提供更精确的局部区域，其中容易发生熔融事件。

公开(公告)号：US07365025B2

公开(公告)日：2008-04-29

申请号：US11348428

申请日：2006-02-06

申请人： Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Oo Kim

发明人： Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Oo Kim

IPC分类号： H01L21/311

CPC分类号： H01L21/76808 ,  H01L21/31144

摘要： Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole.

摘要翻译： 形成集成电路器件的方法包括图案化电绝缘层以支持其中的双镶嵌互连结构。 图案化电绝缘层的步骤包括使用具有不同孔隙特性的多个平坦化层。 在集成电路器件内形成互连结构可以包括在衬底上形成电绝缘层，并形成至少部分穿过电绝缘层延伸的至少一个通孔。 至少一个通孔填充有具有第一孔隙率的第一电绝缘材料。 填充的至少一个通孔然后被具有低于第一孔隙率的第二孔隙率的第二电绝缘材料层覆盖。 选择性地回蚀第二电绝缘材料层以暴露至少一个通孔中的第一电绝缘材料的第一部分。 电绝缘层被选择性蚀刻以在其中限定其中的沟槽，其暴露出至少一个通孔中的第一电绝缘材料的第二部分。

公开(公告)号：US07306996B2

公开(公告)日：2007-12-11

申请号：US11498197

申请日：2006-08-03

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

摘要翻译： 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是使用H 2 H 2 O和H 2 H 2的分压的H氧化方法 2极化气氛，以便在抑制可能包含在金属栅极图案中的金属层的氧化的同时氧化基板和金属栅极图案的部分。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。