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    Process for forming field isolation and a structure over a semiconductor substrate
    3.
    发明授权
    Process for forming field isolation and a structure over a semiconductor substrate 失效
    用于形成场隔离的工艺和半导体衬底上的结构

    公开(公告)号：US5580815A

    公开(公告)日：1996-12-03

    申请号：US200029

    申请日：1994-02-22

    申请人： Ting C. Hsu ,  Laureen H. Parker ,  David G. Kolar ,  Philip J. Tobin ,  Hsing-Huang Tseng ,  Lisa K. Garling ,  Vida Ilderem

    发明人： Ting C. Hsu ,  Laureen H. Parker ,  David G. Kolar ,  Philip J. Tobin ,  Hsing-Huang Tseng ,  Lisa K. Garling ,  Vida Ilderem

    IPC分类号： H01L21/32 ,  H01L21/76

    CPC分类号： H01L21/32

    摘要： An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous silicon layer helps to reduce encroachment compared to conventional LOCOS field isolation process and helps to reduce the likelihood of forming pits within a substrate compared to a PBL field isolation process. The annealed amorphous silicon layer may be used in forming field isolation regions that defines the active regions between transistors including MOSFETs and bipolar transistors. Doped silicon or a silicon-rich silicon nitride layer may be used in place of conventional materials. The anneal of the amorphous silicon layer may be performed after forming a silicon nitride layer if the silicon nitride layer is deposited at a temperature no higher than 600 degrees Celsius.

    摘要翻译： 在LOCOS场隔离工艺中使用时，形成退火的非晶硅层，形成场隔离区。 退火的非晶硅层有助于减少与常规LOCOS场隔离过程相比的侵蚀，并且有助于降低与PBL场隔离工艺相比在衬底内形成凹坑的可能性。 退火的非晶硅层可以用于形成场隔离区域，其限定包括MOSFET和双极晶体管的晶体管之间的有源区。 可以使用掺杂硅或富硅的氮化硅层代替常规材料。 如果在不高于600摄氏度的温度下沉积氮化硅层，则可以在形成氮化硅层之后执行非晶硅层的退火。

    Method for forming a buried contact in a semiconductor device
    4.
    发明授权
    Method for forming a buried contact in a semiconductor device 失效
    在半导体器件中形成埋入触点的方法

    公开(公告)号：US5162259A

    公开(公告)日：1992-11-10

    申请号：US650101

    申请日：1991-02-04

    申请人： David G. Kolar ,  Robert E. Jones

    发明人： David G. Kolar ,  Robert E. Jones

    IPC分类号： H01L21/74 ,  H01L21/768

    CPC分类号： H01L21/76895 ,  H01L21/743

    摘要： A process for forming a buried contact (50) in a semiconductor device (20) which avoids etch damage to the substrate and forms a self-aligned, low resistance contact to a silicon substrate (22) is provided. After forming a contact opening (32) through overlying insulating and conducting layers (24, 28,30), a silicide region (40) is formed in the substrate at the contact surface (34) exposed by the contact opening (32). A refractory metal silicide which provides high etching selectivity to polysilicon is formed in the substrate at the contact surface (34) by either a blanket deposition of a refractory metal into the contact opening (32), or alternatively, by a selective deposition process using contact surface (34) as a nucleation site. In a preferred embodiment, a cobalt or tantalum silicide region (40) is formed in the substrate at the contact surface (34) and a conductive layer (42) is deposited and etched to form an interconnect (48) contacting the silicide region (40). The high etching selectivity obtainable between the conductive layer ( 42) and the silicide region (40) avoids damage to the substrate surface providing improved device performance.

    摘要翻译： 提供了一种用于在半导体器件（20）中形成掩埋触点（50）的工艺，其避免了对衬底的蚀刻损伤并且形成与硅衬底（22）的自对准的低电阻接触。 在通过覆盖的绝缘和导电层（24,28,30）形成接触开口（32）之后，在由接触开口（32）暴露的接触表面（34）处，在衬底中形成硅化物区域（40）。 在接触表面（34）上的基底中通过将难熔金属层压沉积到接触开口（32）中或者通过使用接触的选择性沉积工艺在多孔体中形成对多晶硅提供高蚀刻选择性的难熔金属硅化物 表面（34）作为成核位点。 在优选实施例中，在接触表面（34）处在衬底中形成钴或钽硅化物区（40），并且沉积并蚀刻导电层（42）以形成与硅化物区域（40）接触的互连（48） ）。 可以在导电层（42）和硅化物区域（40）之间获得的高蚀刻选择性避免了损坏衬底表面，从而提供改进的器件性能。

    Process for forming field isolation
    5.
    发明授权
    Process for forming field isolation 失效
    用于形成场隔离的方法

    公开(公告)号：US5707889A

    公开(公告)日：1998-01-13

    申请号：US645362

    申请日：1996-05-13

    申请人： Ting Chen Hsu ,  Laureen H. Parker ,  David G. Kolar ,  Philip J. Tobin ,  Hsing-Huang Tseng ,  Lisa K. Garling ,  Vida Ilderem

    发明人： Ting Chen Hsu ,  Laureen H. Parker ,  David G. Kolar ,  Philip J. Tobin ,  Hsing-Huang Tseng ,  Lisa K. Garling ,  Vida Ilderem

    IPC分类号： H01L21/32 ,  H01L21/76

    CPC分类号： H01L21/32

    摘要： An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous silicon layer helps to reduce encroachment compared to conventional LOCOS field isolation process and helps to reduce the likelihood of forming pits within a substrate compared to a PBL field isolation process. The annealed amorphous silicon layer may be used in forming field isolation regions that defines the active regions between transistors including MOSFETs and bipolar transistors. Doped silicon or a silicon-rich silicon nitride layer may be used in place of conventional materials. The anneal of the amorphous silicon layer may be performed after forming a silicon nitride layer if the silicon nitride layer is deposited at a temperature no higher than 600 degrees Celsius.

    摘要翻译： 在LOCOS场隔离工艺中使用时，形成退火的非晶硅层，形成场隔离区。 退火的非晶硅层有助于减少与常规LOCOS场隔离过程相比的侵蚀，并且有助于降低与PBL场隔离工艺相比在衬底内形成凹坑的可能性。 退火的非晶硅层可以用于形成场隔离区域，其限定包括MOSFET和双极晶体管的晶体管之间的有源区。 可以使用掺杂硅或富硅的氮化硅层代替常规材料。 如果在不高于600摄氏度的温度下沉积氮化硅层，则可以在形成氮化硅层之后执行非晶硅层的退火。