公开(公告)号：US07091074B2

公开(公告)日：2006-08-15

申请号：US10878103

申请日：2004-06-28

申请人： Jae-Jong Han ,  Woo-Sung Lee ,  Sang-Jin Park

发明人： Jae-Jong Han ,  Woo-Sung Lee ,  Sang-Jin Park

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/10894 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873

摘要： A first gate oxide layer pattern having a first thickness is formed in a first region of a substrate and a second gate oxide layer having a second thickness is formed in a second region of a substrate. A surface of the second gate oxide layer is selectively nitrified to form an oxynitride layer, thereby reducing a depletion effect of a poly gate and a fluctuation of threshold voltage.

摘要翻译： 在衬底的第一区域中形成具有第一厚度的第一栅极氧化物层图案，并且在衬底的第二区域中形成具有第二厚度的第二栅极氧化物层。 第二栅极氧化物层的表面被选择性硝化以形成氧氮化物层，从而降低多晶硅栅极的耗尽效应和阈值电压的波动。

公开(公告)号：US20050003597A1

公开(公告)日：2005-01-06

申请号：US10878103

申请日：2004-06-28

申请人： Jae-Jong Han ,  Woo-Sung Lee ,  Sang-Jin Park

发明人： Jae-Jong Han ,  Woo-Sung Lee ,  Sang-Jin Park

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873

摘要： A first gate oxide layer pattern having a first thickness is formed in a first region of a substrate and a second gate oxide layer having a second thickness is formed in a second region of a substrate. A surface of the second gate oxide layer is selectively nitrified to form an oxynitride layer, thereby reducing a depletion effect of a poly gate and a fluctuation of threshold voltage.

摘要翻译： 在衬底的第一区域中形成具有第一厚度的第一栅极氧化物层图案，并且在衬底的第二区域中形成具有第二厚度的第二栅极氧化物层。 第二栅极氧化物层的表面被选择性硝化以形成氧氮化物层，从而降低多晶硅栅极的耗尽效应和阈值电压的波动。

公开(公告)号：US08241979B2

公开(公告)日：2012-08-14

申请号：US12805825

申请日：2010-08-20

申请人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

发明人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

IPC分类号： H01L21/8234

CPC分类号： H01L45/143 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/66204 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.

摘要翻译： 形成垂直二极管的方法和制造半导体器件（例如，诸如相变存储器件的半导体存储器件）的方法包括：在衬底上形成具有开口的绝缘结构，并用非晶硅填充该开口 层。 形成金属硅化物层以接触非晶硅层的至少一部分，然后通过使用金属硅化物层使非晶硅层结晶而在开口中形成多晶硅层。 通过将杂质注入到多晶硅层中形成掺杂多晶硅层。 因此，在开口中形成多晶硅层，而不进行选择性外延生长（SEG）工艺，从而可以提高二极管的电特性。

公开(公告)号：US07803679B2

公开(公告)日：2010-09-28

申请号：US12034440

申请日：2008-02-20

申请人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

发明人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

IPC分类号： H01L29/88

CPC分类号： H01L45/143 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/66204 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.

摘要翻译： 形成垂直二极管的方法和制造半导体器件（例如，诸如相变存储器件的半导体存储器件）的方法包括：在衬底上形成具有开口的绝缘结构，并用非晶硅填充该开口 层。 形成金属硅化物层以接触非晶硅层的至少一部分，然后通过使用金属硅化物层使非晶硅层结晶而在开口中形成多晶硅层。 通过将杂质注入到多晶硅层中形成掺杂多晶硅层。 因此，在开口中形成多晶硅层，而不进行选择性外延生长（SEG）工艺，从而可以提高二极管的电特性。

公开(公告)号：US20100323489A1

公开(公告)日：2010-12-23

申请号：US12805825

申请日：2010-08-20

申请人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

发明人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

IPC分类号： H01L21/02

CPC分类号： H01L45/143 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/66204 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.

公开(公告)号：USD686152S1

公开(公告)日：2013-07-16

申请号：US29428745

申请日：2012-08-02

申请人： Jeong-Seop Lee ,  Myung-Sook Kwon ,  Sang-Jin Park ,  Nam Sunwoo

设计人： Jeong-Seop Lee ,  Myung-Sook Kwon ,  Sang-Jin Park ,  Nam Sunwoo

公开(公告)号：USD684531S1

公开(公告)日：2013-06-18

申请号：US29417929

申请日：2012-04-10

申请人： Dae-Yon Moon ,  Sang-Jin Park

设计人： Dae-Yon Moon ,  Sang-Jin Park

公开(公告)号：USD684530S1

公开(公告)日：2013-06-18

申请号：US29417928

申请日：2012-04-10

申请人： Dae-Yon Moon ,  Sang-Jin Park

设计人： Dae-Yon Moon ,  Sang-Jin Park

公开(公告)号：US20130095364A1

公开(公告)日：2013-04-18

申请号：US13475838

申请日：2012-05-18

申请人： Jun-Sun Yong ,  Chang-Seob Kim ,  Sang-Jin Lee ,  Sae-Weon Roh ,  Sang-Jin Park

发明人： Jun-Sun Yong ,  Chang-Seob Kim ,  Sang-Jin Lee ,  Sae-Weon Roh ,  Sang-Jin Park

IPC分类号： H01M2/30 ,  H01M10/50 ,  H01M2/02

CPC分类号： H01M2/02 ,  H01M2/04 ,  H01M2/0404 ,  H01M2/0473 ,  H01M2/06 ,  H01M2/30 ,  H01M2/34

摘要： A secondary battery including: an electrode assembly; a case containing the electrode assembly; a cap plate covering an opening of the case; a safety device on the cap plate and including a first lead; and an electrode terminal electrically connecting the electrode assembly and the first lead, the cap plate including a conductive member and an insulating portion, and the first lead is supported on the insulating portion, and the conductive member and the insulating portion being integrally formed.

摘要翻译： 一种二次电池，包括：电极组件; 包含电极组件的壳体; 覆盖所述壳体的开口的盖板; 盖板上的安全装置，包括第一引线; 以及电极端子，其电连接所述电极组件和所述第一引线，所述盖板包括导电构件和绝缘部，所述第一引线被支撑在所述绝缘部上，并且所述导电构件和所述绝缘部一体地形成。

公开(公告)号：US08039900B2

公开(公告)日：2011-10-18

申请号：US11823765

申请日：2007-06-28

申请人： Kyoung-Seok Kim ,  Kong-Soo Lee ,  Sang-Jin Park ,  Sung-Kwan Kang ,  Ko-Eun Lee

发明人： Kyoung-Seok Kim ,  Kong-Soo Lee ,  Sang-Jin Park ,  Sung-Kwan Kang ,  Ko-Eun Lee

IPC分类号： H01L29/66

CPC分类号： H01L27/0688 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28556 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/8221 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108

摘要： The stacked semiconductor device includes a semiconductor substrate, a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, an active layer pattern formed on each of the insulation layer patterns, a first plug including single crystalline silicon-germanium, a second plug including single crystalline silicon, and a wiring electrically connected to the first plug and sufficiently filling up the opening. The insulation layer patterns are vertically stacked on the semiconductor substrate and the opening exposes an upper face of the semiconductor substrate. A side portion of the active layer pattern is exposed by the opening. The first plug is formed on the upper face of the semiconductor substrate to partially fill the opening. The second plug is partially formed on the first plug, and has substantially the same interface as that of the first plug.

摘要翻译： 叠层半导体器件包括半导体衬底，具有至少两个绝缘层图案和开口的多层绝缘层图案，形成在每个绝缘层图案上的有源层图案，包括单晶硅锗的第一插头， 包括单晶硅的第二插头和电连接到第一插头并充分填满开口的布线。 绝缘层图案垂直堆叠在半导体衬底上，并且开口暴露半导体衬底的上表面。 有源层图案的侧面部分由开口露出。 第一插头形成在半导体衬底的上表面上以部分地填充开口。 第二插头部分地形成在第一插头上，并且具有与第一插头基本相同的界面。