公开(公告)号：US06673706B2

公开(公告)日：2004-01-06

申请号：US10023982

申请日：2001-12-21

申请人： Ji-yong Yoo ,  Dae-youp Lee ,  Jeung-woo Lee ,  Suk-joo Lee ,  Jae-han Lee

发明人： Ji-yong Yoo ,  Dae-youp Lee ,  Jeung-woo Lee ,  Suk-joo Lee ,  Jae-han Lee

IPC分类号： H01L213205

CPC分类号： H01L21/0274 ,  G03F7/0035 ,  H01L21/76802 ,  H01L21/76829

摘要： A photoresist pattern is formed, without being exposed, by using photoresist having a residual layer proportion characteristic by which the photoresist dissolves at a suitable rate in a developing solution. First, a target layer to be patterned and a photoresist layer are sequentially formed on a substrate having a pattern that defines a step on the substrate. Some of the photoresist layer is treated with the developing solution, to thereby form a photoresist pattern whose upper surface is situated beneath the step and hence, exposes part of the target layer. Next, the exposed part of the target layer, and the photoresist pattern are removed. A silicidation process may be carried out thereafter on the area(s) from which the target layer has been removed. The method is relatively simple because it does not involve an exposure process. Furthermore, the method can be used to manufacture devices having very fine linewidths, i.e., a small design rule, because it is not subject to the misalignment errors which can occur during a conventional exposure process.

摘要翻译： 通过使用具有残留层比例特性的光致抗蚀剂形成光致抗蚀剂图案，其中光致抗蚀剂以合适的速率溶解在显影溶液中。 首先，在具有限定基板上的台阶的图案的基板上依次形成待图案化的目标层和光致抗蚀剂层。 用显影液处理一些光致抗蚀剂层，从而形成上表面位于台阶之下的光致抗蚀剂图案，从而露出目标层的一部分。 接下来，去除目标层的曝光部分和光刻胶图案。 此后可以在去除了目标层的区域上进行硅化处理。 该方法相对简单，因为它不涉及曝光过程。 此外，该方法可以用于制造具有非常细线宽的装置，即小的设计规则，因为它不会受到常规曝光过程中可能发生的未对准误差的影响。

公开(公告)号：US06620690B2

公开(公告)日：2003-09-16

申请号：US10196128

申请日：2002-07-17

申请人： Jae-han Lee ,  Dae-youp Lee

发明人： Jae-han Lee ,  Dae-youp Lee

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536 ,  H01L27/11543

摘要： A method of fabricating a flash memory device uses a self-aligned non-exposure pattern formation process. A conductive layer and an oxidation-blocking layer are formed on a stepped pattern including a floating gate pattern and an inter-gate insulating layer pattern such that the conductive layer and the oxidation-blocking layer conform to the stepped pattern. A photoresist layer is formed on the oxidation-blocking layer such that the photoresist layer has an upper surface situated above the oxidation-blocking layer. A portion of the photoresist layer is dissolved, without having photo-exposed the photoresist layer, by soaking the photoresist layer in developing solution. This soaking alone, or supplemented with an etch back process, is carried out until the upper surface of the photoresist layer is situated below the upper surface of the oxidation-blocking layer on the stepped pattern. The resulting photoresist pattern exposes that part of the oxidation-blocking layer on the stepped pattern. A blocking layer pattern exposing the conductive layer is formed on the stepped pattern by removing the exposed part of the oxidation-blocking layer. The photoresist pattern is then removed. A hard mask defining a control gate is formed by oxidizing the surface of the conductive layer exposed by the blocking layer pattern. The blocking layer pattern is then removed. A control gate is formed by etching the conductive layer using the hard mask as an etch mask. The hard mask is then removed whereupon a stacked gate structure is formed.

摘要翻译： 一种制造闪存器件的方法使用自对准非曝光图案形成工艺。 导电层和氧化阻挡层形成在包括浮栅图案和栅间绝缘层图案的台阶图案上，使得导电层和氧化阻挡层符合阶梯图案。 在氧化阻挡层上形成光致抗蚀剂层，使得光致抗蚀剂层具有位于氧化阻挡层上方的上表面。 光致抗蚀剂层的一部分通过将光致抗蚀剂层浸泡在显影溶液中而不曝光光致抗蚀剂层而溶解。 单独浸渍或补充有回蚀工艺，直到光致抗蚀剂层的上表面位于阶梯图案上的氧化阻挡层的上表面之下。 所得到的光致抗蚀剂图案将该部分氧化阻挡层暴露在台阶图案上。 通过去除氧化阻挡层的暴露部分，在阶梯形图案上形成露出导电层的阻挡层图案。 然后去除光致抗蚀剂图案。 通过氧化由阻挡层图案暴露的导电层的表面来形成限定控制栅极的硬掩模。 然后去除阻挡层图案。 通过使用硬掩模作为蚀刻掩模蚀刻导电层来形成控制栅极。 然后去除硬掩模，从而形成堆叠的栅极结构。

公开(公告)号：US20130171821A1

公开(公告)日：2013-07-04

申请号：US13485230

申请日：2012-05-31

申请人： Bong-cheol Kim ,  Dae-youp Lee

发明人： Bong-cheol Kim ,  Dae-youp Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L27/10894 ,  H01L27/11529

摘要： Metal contacts are formed within a string overhead area using a double patterning technology (DPT) process thereby allowing for the reduction of a string overhead area and a concomitant reduction in the chip size of a semiconductor device. A first mask pattern is formed by etching a first mask layer, the first mask pattern including a first opening formed in a cell region and a first hole formed in a peripheral region. A first sacrificial pattern is formed on the first mask pattern and the exposed first insulating layer of the cell region using a double patterning technology process. Contact holes are formed by exposing the target layer by etching the first insulating layer using the first mask pattern and the first sacrificial pattern as an etch mask. Metal contacts are then formed in the contact holes.

摘要翻译： 金属触点使用双重图案化技术（DPT）工艺形成在串联架构区域内，从而允许减少串联开销区域并伴随减小半导体器件的芯片尺寸。 通过蚀刻第一掩模层形成第一掩模图案，第一掩模图案包括形成在单元区域中的第一开口和形成在周边区域中的第一孔。 使用双重图案化技术工艺在第一掩模图案和单元区域的暴露的第一绝缘层上形成第一牺牲图案。 通过使用第一掩模图案和第一牺牲图案作为蚀刻掩模蚀刻第一绝缘层来暴露目标层来形成接触孔。 然后在接触孔中形成金属接触。

公开(公告)号：US08227354B2

公开(公告)日：2012-07-24

申请号：US12480807

申请日：2009-06-09

申请人： Bong-cheol Kim ,  Dae-youp Lee ,  Sang-youn Jo ,  Ja-min Koo ,  Byeong-hwan Son ,  Jang-hwan Jeong

发明人： Bong-cheol Kim ,  Dae-youp Lee ,  Sang-youn Jo ,  Ja-min Koo ,  Byeong-hwan Son ,  Jang-hwan Jeong

IPC分类号： H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11521

摘要： Provided is a method of forming patterns of a semiconductor device, whereby patterns having various widths can be simultaneously formed, and pattern density can be doubled by a double patterning process in a portion of the semiconductor device. In the method of forming patterns of a semiconductor device, a first mold mask pattern and a second mold mask patter having different widths are formed on a substrate. A pair of first spacers covering both sidewalls of the first mold mask pattern and a pair of second spacers covering both sidewalls of the second mold mask pattern are formed. The first mold mask pattern and the second mold mask pattern are removed, and a wide-width mask pattern covering the second spacer is formed. A lower layer is etched using the first spacers, the second spacers, and the wide-width mask pattern as an etch mask.

摘要翻译： 提供了一种形成半导体器件的图案的方法，由此可以同时形成具有各种宽度的图案，并且通过在半导体器件的一部分中的双重图案化工艺可以使图案密度加倍。 在形成半导体器件的图案的方法中，在衬底上形成具有不同宽度的第一模具掩模图案和第二模具掩模图案。 形成覆盖第一模具掩模图案的两个侧壁的一对第一间隔件和覆盖第二模具掩模图案的两个侧壁的一对第二间隔件。 去除第一模具掩模图案和第二模具掩模图案，并且形成覆盖第二间隔件的宽幅掩模图案。 使用第一间隔物，第二间隔物和宽幅掩模图案作为蚀刻掩模蚀刻下层。

公开(公告)号：US06841338B2

公开(公告)日：2005-01-11

申请号：US10173375

申请日：2002-06-17

申请人： Dae-youp Lee ,  Jeong-lim Nam ,  Do-yul Yoo ,  Jeung-woo Lee

发明人： Dae-youp Lee ,  Jeong-lim Nam ,  Do-yul Yoo ,  Jeung-woo Lee

IPC分类号： C08F212/14 ,  G03F1/14 ,  G03F7/004 ,  G03F7/039 ,  G03F7/30 ,  G03F7/32 ,  G03F7/40 ,  H01L21/027 ,  G03C5/00

CPC分类号： G03F7/0392 ,  G03F1/50

摘要： A photoresist composition may include formulas 1 and 2:  where R is an acetal group or a ter-butyloxy carbonyl (t-BOC) group, n and m are integers, n/(m+n) is 0.01−0.8, and m/(m+n) is 1−[n/(m+n)],  where r is an integer between 8-40. A method for forming photoresist patterns may include forming a photoresist layer on a semiconductor substrate and exposing and developing the photoresist layer using a mask pattern that includes first areas having a light transmissivity of about 100% and second areas having a light transmissivity of between about 10% and about 30%.

摘要翻译： 光致抗蚀剂组合物可以包括式1和2：其中R是缩醛基或叔丁氧基羰基（t-BOC）基团，n和m是整数，n /（m + n）是0.01-0.8，m / （m + n）是1- [n /（m + n）]，其中r是8-40之间的整数。一种用于形成光致抗蚀剂图案的方法可以包括在半导体衬底上形成光致抗蚀剂层并曝光和显影光致抗蚀剂 层，其使用包括具有约100％的光透射率的第一区域和具有约10％至约30％的透光率的第二区域的掩模图案。

公开(公告)号：US08361905B2

公开(公告)日：2013-01-29

申请号：US12581298

申请日：2009-10-19

申请人： Bong-cheol Kim ,  Dae-youp Lee ,  Hyun-woo Kim ,  Young-moon Choi ,  Jong-su Park ,  Byeong-hwan Son

发明人： Bong-cheol Kim ,  Dae-youp Lee ,  Hyun-woo Kim ,  Young-moon Choi ,  Jong-su Park ,  Byeong-hwan Son

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/311

CPC分类号： H01L21/76229 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526

摘要： Provided are methods of forming patterns of semiconductor devices, whereby patterns having various widths may be simultaneously formed, and a pattern density may be doubled by a double patterning process in a portion of the semiconductor device. A dual mask layer is formed on a substrate. A variable mask layer is formed on the dual mask layer. A first photoresist pattern having a first thickness and a first width in the first region, and a second photoresist pattern having a second thickness greater than the first thickness and a second width wider than the first width in the second region are formed on the variable mask layer. A first mask pattern and a first variable mask pattern are formed in the first region, and a second mask pattern and a second variable mask pattern are formed in the second region, by sequentially etching the variable mask layer and the dual mask layer by using, as etch masks, the first photoresist pattern and the second photoresist pattern. First spacers covering side walls of the first mask pattern and second spacers covering side walls of the second mask pattern are formed. The first mask pattern is removed, and then the substrate is etched in the first region and the second region by using the first spacers as an etch mask in the first region, and the second mask pattern and the second spacers as an etch mask in the second region.

摘要翻译： 提供了形成半导体器件的图案的方法，由此可以同时形成具有各种宽度的图案，并且在半导体器件的一部分中通过双重图案化工艺可以使图案密度加倍。 在基板上形成双掩模层。 在双掩模层上形成可变掩模层。 在第一区域中具有第一厚度和第一宽度的第一光致抗蚀剂图案和具有大于第一厚度的第二厚度的第二光致抗蚀剂图案和宽于第二区域中的第一宽度的第二宽度形成在可变掩模 层。 在第一区域中形成第一掩模图案和第一可变掩模图案，并且通过使用可变掩模层和双掩模层依次蚀刻第二区域中的第二掩模图案和第二可变掩模图案， 作为蚀刻掩模，第一光致抗蚀剂图案和第二光致抗蚀剂图案。 形成覆盖第一掩模图案的侧壁的第一间隔物和覆盖第二掩模图案的侧壁的第二间隔物。 去除第一掩模图案，然后通过在第一区域中使用第一间隔物作为蚀刻掩模在第一区域和第二区域中蚀刻衬底，并且在第二区域中将第二掩模图案和第二间隔物作为蚀刻掩模 第二区。

公开(公告)号：US20100240221A1

公开(公告)日：2010-09-23

申请号：US12581298

申请日：2009-10-19

申请人： Bong-cheol Kim ,  Dae-youp Lee ,  Hyun-Woo Kim ,  Young-moon Choi ,  Jong-su Park ,  Byeong-hwan Son

发明人： Bong-cheol Kim ,  Dae-youp Lee ,  Hyun-Woo Kim ,  Young-moon Choi ,  Jong-su Park ,  Byeong-hwan Son

IPC分类号： H01L21/306

CPC分类号： H01L21/76229 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526

摘要： Provided are methods of forming patterns of semiconductor devices, whereby patterns having various widths may be simultaneously formed, and a pattern density may be doubled by a double patterning process in a portion of the semiconductor device. A dual mask layer is formed on a substrate. A variable mask layer is formed on the dual mask layer. A first photoresist pattern having a first thickness and a first width in the first region, and a second photoresist pattern having a second thickness greater than the first thickness and a second width wider than the first width in the second region are formed on the variable mask layer. A first mask pattern and a first variable mask pattern are formed in the first region, and a second mask pattern and a second variable mask pattern are formed in the second region, by sequentially etching the variable mask layer and the dual mask layer by using, as etch masks, the first photoresist pattern and the second photoresist pattern. First spacers covering side walls of the first mask pattern and second spacers covering side walls of the second mask pattern are formed. The first mask pattern is removed, and then the substrate is etched in the first region and the second region by using the first spacers as an etch mask in the first region, and the second mask pattern and the second spacers as an etch mask in the second region.

摘要翻译： 提供了形成半导体器件的图案的方法，由此可以同时形成具有各种宽度的图案，并且在半导体器件的一部分中通过双重图案化工艺可以使图案密度加倍。 在基板上形成双掩模层。 在双掩模层上形成可变掩模层。 在第一区域中具有第一厚度和第一宽度的第一光致抗蚀剂图案和具有大于第一厚度的第二厚度的第二光致抗蚀剂图案和宽于第二区域中的第一宽度的第二宽度形成在可变掩模 层。 在第一区域中形成第一掩模图案和第一可变掩模图案，并且通过使用可变掩模层和双掩模层依次蚀刻第二区域中的第二掩模图案和第二可变掩模图案， 作为蚀刻掩模，第一光致抗蚀剂图案和第二光致抗蚀剂图案。 形成覆盖第一掩模图案的侧壁的第一间隔物和覆盖第二掩模图案的侧壁的第二间隔物。 去除第一掩模图案，然后通过在第一区域中使用第一间隔物作为蚀刻掩模在第一区域和第二区域中蚀刻衬底，并且在第二区域中将第二掩模图案和第二间隔物作为蚀刻掩模 第二区。

公开(公告)号：US20100149502A1

公开(公告)日：2010-06-17

申请号：US12458503

申请日：2009-07-14

申请人： Jin-seok Heo ,  Jin-hong Park ,  Dae-youp Lee ,  Jeong-ho Yeo

发明人： Jin-seok Heo ,  Jin-hong Park ,  Dae-youp Lee ,  Jeong-ho Yeo

IPC分类号： G03B27/42

CPC分类号： G03B27/42

摘要： A method of detecting reticle error may include using an optical source of an exposure unit to cause light to be incident on a reticle installed in the exposure unit, and detecting the reticle error using only 0th diffraction light from among diffraction lights transmitted through the reticle. A method of detecting reticle error may include: installing a reticle, including a mask substrate and mask patterns having a critical dimension formed on the mask substrate, in an exposure unit to cause light to be incident on the reticle; exposing a photoresist film disposed on a wafer in the exposure unit using only 0th diffraction light from among diffraction lights transmitted through the reticle; developing the exposed photoresist film; and analyzing a thickness change, an image, or the thickness change and image of the developed photoresist film, in order to detect the reticle error at a wafer level.

摘要翻译： 检测标线错误的方法可以包括使用曝光单元的光源使光入射到安装在曝光单元中的掩模版上，并且仅使用通过掩模版传播的衍射光中的第0衍射光来检测标线误差。 检测标线错误的方法可以包括：在曝光单元中安装包括掩模基板的掩模版和具有形成在掩模基板上的临界尺寸的掩模图案，以使光入射到掩模版上; 使用透射通过掩模版的衍射光中的第0衍射光曝光设置在曝光单元中的晶片上的光致抗蚀剂膜; 显影曝光的光致抗蚀剂膜; 并分析显影的光刻胶膜的厚度变化，图像或厚度变化和图像，以便检测晶片级的标线误差。

公开(公告)号：US08546258B2

公开(公告)日：2013-10-01

申请号：US13485230

申请日：2012-05-31

申请人： Bong-cheol Kim ,  Dae-youp Lee

发明人： Bong-cheol Kim ,  Dae-youp Lee

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L27/10894 ,  H01L27/11529

摘要： Metal contacts are formed within a string overhead area using a double patterning technology (DPT) process thereby allowing for the reduction of a string overhead area and a concomitant reduction in the chip size of a semiconductor device. A first mask pattern is formed by etching a first mask layer, the first mask pattern including a first opening formed in a cell region and a first hole formed in a peripheral region. A first sacrificial pattern is formed on the first mask pattern and the exposed first insulating layer of the cell region using a double patterning technology process. Contact holes are formed by exposing the target layer by etching the first insulating layer using the first mask pattern and the first sacrificial pattern as an etch mask. Metal contacts are then formed in the contact holes.

摘要翻译： 金属触点使用双重图案化技术（DPT）工艺形成在串联架构区域内，从而允许减少串联开销区域并伴随减小半导体器件的芯片尺寸。 通过蚀刻第一掩模层形成第一掩模图案，第一掩模图案包括形成在单元区域中的第一开口和形成在周边区域中的第一孔。 使用双重图案化技术工艺在第一掩模图案和单元区域的暴露的第一绝缘层上形成第一牺牲图案。 通过使用第一掩模图案和第一牺牲图案作为蚀刻掩模蚀刻第一绝缘层来暴露目标层来形成接触孔。 然后在接触孔中形成金属接触。

公开(公告)号：US08384876B2

公开(公告)日：2013-02-26

申请号：US12458503

申请日：2009-07-14

申请人： Jin-seok Heo ,  Jin-hong Park ,  Dae-youp Lee ,  Jeong-ho Yeo

发明人： Jin-seok Heo ,  Jin-hong Park ,  Dae-youp Lee ,  Jeong-ho Yeo

IPC分类号： G03B27/68

CPC分类号： G03B27/42

摘要： A method of detecting reticle error may include using an optical source of an exposure unit to cause light to be incident on a reticle installed in the exposure unit, and detecting the reticle error using only 0th diffraction light from among diffraction lights transmitted through the reticle. A method of detecting reticle error may include: installing a reticle, including a mask substrate and mask patterns having a critical dimension formed on the mask substrate, in an exposure unit to cause light to be incident on the reticle; exposing a photoresist film disposed on a wafer in the exposure unit using only 0th diffraction light from among diffraction lights transmitted through the reticle; developing the exposed photoresist film; and analyzing a thickness change, an image, or the thickness change and image of the developed photoresist film, in order to detect the reticle error at a wafer level.

摘要翻译： 检测标线错误的方法可以包括使用曝光单元的光源使光入射到安装在曝光单元中的掩模版上，并且仅使用通过掩模版传播的衍射光中的第0衍射光来检测标线误差。 检测标线错误的方法可以包括：在曝光单元中安装包括掩模基板的掩模版和具有形成在掩模基板上的临界尺寸的掩模图案，以使光入射到掩模版上; 使用透射通过掩模版的衍射光中的第0衍射光曝光设置在曝光单元中的晶片上的光致抗蚀剂膜; 显影曝光的光致抗蚀剂膜; 并分析显影的光刻胶膜的厚度变化，图像或厚度变化和图像，以便检测晶片级的标线误差。