公开(公告)号：US08443122B2

公开(公告)日：2013-05-14

申请号：US12917854

申请日：2010-11-02

申请人： JaeGeun Yun ,  Junhyung Um ,  Woo-Cheol Kwon ,  Hyun-Joon Kang ,  Bub-chul Jeong

发明人： JaeGeun Yun ,  Junhyung Um ,  Woo-Cheol Kwon ,  Hyun-Joon Kang ,  Bub-chul Jeong

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F13/4059

摘要： An asynchronous upsizing circuit in a data processing system. The asynchronous upsizing circuit includes an asynchronous packer and an asynchronous unpacker. The asynchronous packer includes a write buffer commonly used for an asynchronous bridge and for upsizing and for buffering a write channel data; and first and second asynchronous packing controllers controlling channel compaction according to first and second clocks, respectively, regarding the write channel data inputted/outputted to/from the write buffer during a burst write operation. The asynchronous unpacker includes a read buffer commonly used for an asynchronous bridge and for upsizing and for buffering a read channel data; and first and second asynchronous unpacking controllers controlling channel compaction according to the first and second clocks, respectively, regarding the read channel data inputted/outputted to/from the read buffer during a burst read operation.

摘要翻译： 数据处理系统中的异步增大电路。 异步升压电路包括异步封隔器和异步解包器。 异步封隔器包括通常用于异步桥的写入缓冲器，并且用于增大和缓冲写通道数据; 以及第一和第二异步打包控制器，分别根据第一和第二时钟控制在突发写入操作期间输入/输出到写入缓冲器的写入通道数据的通道压缩。 异步解包器包括通常用于异步网桥的读缓冲器，并用于增大和缓冲读通道数据; 以及分别针对在突发读取操作期间从读取缓冲器输入/输出的读通道数据，分别根据第一和第二时钟控制信道压缩的第一和第二异步解包控制器。

公开(公告)号：US20120131246A1

公开(公告)日：2012-05-24

申请号：US13276748

申请日：2011-10-19

申请人： Bub-chul Jeong ,  Jaegeun Yun ,  Junhyung Um ,  Jung-Sik Lee ,  Hyun-Joon Kang ,  Sung-Min Hong ,  Ling Ling Liao

发明人： Bub-chul Jeong ,  Jaegeun Yun ,  Junhyung Um ,  Jung-Sik Lee ,  Hyun-Joon Kang ,  Sung-Min Hong ,  Ling Ling Liao

IPC分类号： G06F13/00

CPC分类号： G06F13/4217 ,  G06F2213/0038

摘要： A system-on-a-chip semiconductor device comprises a first master device configured to issue a request having a transaction ID, a plurality of slave devices configured to provide data in response to the request, and an interconnector configured to include a slave interface for providing the request to one or more master interfaces and for supplying response data to the first master device based on operation characteristics of the first master.An arbitration method of an interconnector transferring a plurality of response data provided from a plurality of slave devices to a master device comprises selecting one of a plurality of arbitration modes based on operation characteristics of the master device; and transferring the response data in the order determined by transfer priority corresponding to the selected arbitration mode.

摘要翻译： 片上系统半导体器件包括被配置为发出具有事务ID的请求的第一主设备，被配置为响应于该请求而提供数据的多个从设备，以及互连器，被配置为包括从接口， 向所述主接口提供所述请求，并且基于所述第一主设备的操作特性向所述第一主设备提供响应数据。 将从多个从设备提供的多个响应数据传送到主设备的互连器的仲裁方法包括基于主设备的操作特性选择多个仲裁模式中的一个; 并以与所选仲裁模式对应的传送优先级确定的顺序传送响应数据。

公开(公告)号：US20120089758A1

公开(公告)日：2012-04-12

申请号：US13178666

申请日：2011-07-08

申请人： Jaegeun Yun ,  Bub-chul Jeong ,  Junhyung Um ,  Hyun-Joon Kang ,  Sung-Min Hong ,  LIAOLINGLING

发明人： Jaegeun Yun ,  Bub-chul Jeong ,  Junhyung Um ,  Hyun-Joon Kang ,  Sung-Min Hong ,  LIAOLINGLING

IPC分类号： G06F13/00

CPC分类号： G06F13/4022

摘要： At least one example embodiment discloses a System on Chip (SoC). The SoC includes a master block, a plurality of slave blocks configured to operate in response to a request from the master block, and an interconnect block configured to deliver transactions occurring in the master block to the plurality of slave blocks through a plurality of transfer paths. The interconnect block is configured to monitor load information of the plurality of transfer paths and select one of the plurality of transfer paths according to the load information.

摘要翻译： 至少一个示例性实施例公开了片上系统（SoC）。 SoC包括主块，被配置为响应于来自主块的请求而操作的多个从块，以及被配置为通过多个传输路径将在主块中发生的事务传递到多个从块的互连块 。 互连块被配置为监视多个传送路径的负载信息，并且根据负载信息选择多个传送路径中的一个。

公开(公告)号：US08819310B2

公开(公告)日：2014-08-26

申请号：US13276748

申请日：2011-10-19

申请人： Bub-chul Jeong ,  Jaegeun Yun ,  Junhyung Um ,  Jung-Sik Lee ,  Hyun-Joon Kang ,  Sung-Min Hong ,  Ling Ling Liao

发明人： Bub-chul Jeong ,  Jaegeun Yun ,  Junhyung Um ,  Jung-Sik Lee ,  Hyun-Joon Kang ,  Sung-Min Hong ,  Ling Ling Liao

IPC分类号： G06F13/00 ,  G06F13/42

CPC分类号： G06F13/4217 ,  G06F2213/0038

摘要： A system-on-a-chip semiconductor device comprises a first master device configured to issue a request having a transaction ID, a plurality of slave devices configured to provide data in response to the request, and an interconnector configured to include a slave interface for providing the request to one or more master interfaces and for supplying response data to the first master device based on operation characteristics of the first master.An arbitration method of an interconnector transferring a plurality of response data provided from a plurality of slave devices to a master device comprises selecting one of a plurality of arbitration modes based on operation characteristics of the master device; and transferring the response data in the order determined by transfer priority corresponding to the selected arbitration mode.

摘要翻译： 片上系统半导体器件包括被配置为发出具有事务ID的请求的第一主设备，被配置为响应于该请求而提供数据的多个从设备，以及互连器，被配置为包括从接口， 向所述主接口提供所述请求，并且基于所述第一主设备的操作特性向所述第一主设备提供响应数据。 将从多个从设备提供的多个响应数据传送到主设备的互连器的仲裁方法包括基于主设备的操作特性选择多个仲裁模式中的一个; 并以与所选仲裁模式对应的传送优先级确定的顺序传送响应数据。

公开(公告)号：US20110131350A1

公开(公告)日：2011-06-02

申请号：US12917854

申请日：2010-11-02

申请人： JaeGeun Yun ,  Junhyung Um ,  WooCheol Kwon ,  Hyun-Joon Kang ,  Bub-chul Jeong

发明人： JaeGeun Yun ,  Junhyung Um ,  WooCheol Kwon ,  Hyun-Joon Kang ,  Bub-chul Jeong

IPC分类号： G06F5/00 ,  G06F13/00

CPC分类号： G06F13/4059

摘要： An asynchronous upsizing circuit in a data processing system. The asynchronous upsizing circuit includes an asynchronous packer and an asynchronous unpacker. The asynchronous packer includes a write buffer commonly used for an asynchronous bridge and for upsizing and for buffering a write channel data; and first and second asynchronous packing controllers controlling channel compaction according to first and second clocks, respectively, regarding the write channel data inputted/outputted to/from the write buffer during a burst write operation. The asynchronous unpacker includes a read buffer commonly used for an asynchronous bridge and for upsizing and for buffering a read channel data; and first and second asynchronous unpacking controllers controlling channel compaction according to the first and second clocks, respectively, regarding the read channel data inputted/outputted to/from the read buffer during a burst read operation.

摘要翻译： 数据处理系统中的异步增大电路。 异步升压电路包括异步封隔器和异步解包器。 异步封隔器包括通常用于异步桥的写入缓冲器，并且用于增大和缓冲写通道数据; 以及第一和第二异步打包控制器，分别根据第一和第二时钟控制在突发写入操作期间输入/输出到写入缓冲器的写入通道数据的通道压缩。 异步解包器包括通常用于异步网桥的读缓冲器，并用于增大和缓冲读通道数据; 以及分别针对在突发读取操作期间从读取缓冲器输入/输出的读通道数据，分别根据第一和第二时钟控制信道压缩的第一和第二异步解包控制器。

公开(公告)号：US08582709B2

公开(公告)日：2013-11-12

申请号：US12896213

申请日：2010-10-01

申请人： Jaegeun Yun ,  Hyunuk Jung ,  Junhyung Um ,  Sunghoon Shim ,  Sung-Min Hong ,  Bub-chul Jeong

发明人： Jaegeun Yun ,  Hyunuk Jung ,  Junhyung Um ,  Sunghoon Shim ,  Sung-Min Hong ,  Bub-chul Jeong

IPC分类号： H04L7/04

CPC分类号： G06F13/405

摘要： Example embodiments are directed to a bandwidth synchronization circuit and a bandwidth synchronization method. The bandwidth synchronization circuit includes an upsizer and a syncdown unit. The upsizer includes a sync packer and a sync unpacker operating according to a first clock. The syncdown unit is connected to the upsizer and performs a syncdown operation on data of the upsizer in response to a second clock of a frequency lower than a frequency of the first clock.

摘要翻译： 示例性实施例涉及带宽同步电路和带宽同步方法。 带宽同步电路包括升压器和同步单元。 升压器包括根据第一时钟操作的同步封隔器和同步解包器。 所述同步化单元连接到所述升压器，并响应于低于所述第一时钟的频率的频率的第二时钟对所述加大器的数据执行同步操作。

公开(公告)号：US20110122982A1

公开(公告)日：2011-05-26

申请号：US12896213

申请日：2010-10-01

申请人： Jaegeun Yun ,  Hyunuk Jung ,  Junhyung Um ,  Sunghoon Shim ,  Sung-Min Hong ,  Bub-chul Jeong

发明人： Jaegeun Yun ,  Hyunuk Jung ,  Junhyung Um ,  Sunghoon Shim ,  Sung-Min Hong ,  Bub-chul Jeong

IPC分类号： H04L7/04

CPC分类号： G06F13/405

摘要： Example embodiments are directed to a bandwidth synchronization circuit and a bandwidth synchronization method. The bandwidth synchronization circuit includes an upsizer and a syncdown unit. The upsizer includes a sync packer and a sync unpacker operating according to a first clock. The syncdown unit is connected to the upsizer and performs a syncdown operation on data of the upsizer in response to a second clock of a frequency lower than a frequency of the first clock.

摘要翻译： 示例性实施例涉及带宽同步电路和带宽同步方法。 带宽同步电路包括升压器和同步单元。 升压器包括根据第一时钟操作的同步封隔器和同步解包器。 所述同步化单元连接到所述升压器，并响应于低于所述第一时钟的频率的频率的第二时钟对所述加大器的数据执行同步操作。

公开(公告)号：US09152213B2

公开(公告)日：2015-10-06

申请号：US13556545

申请日：2012-07-24

申请人： Jaegeun Yun ,  Lingling Liao ,  Bub-chul Jeong

发明人： Jaegeun Yun ,  Lingling Liao ,  Bub-chul Jeong

IPC分类号： G06F1/32 ,  G06F1/10 ,  G06F13/40

CPC分类号： G06F13/4291 ,  G06F1/10 ,  G06F1/3237 ,  G06F13/28 ,  G06F13/364 ,  G06F13/405 ,  G06F13/4054 ,  G06F2213/0038 ,  Y02B70/12 ,  Y02B70/123 ,  Y02D10/128 ,  Y02D10/151

摘要： A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

摘要翻译： 一种片上系统总线系统，包括：总线，被配置为将片上系统的功能块彼此连接;以及时钟门控单元，连接到总线的接口单元，并且被配置为基本上对在 根据事务检测信号的状态来操作安装在总线上的总线桥装置。

公开(公告)号：US20120215955A1

公开(公告)日：2012-08-23

申请号：US13396155

申请日：2012-02-14

申请人： Jaegeun Yun ,  Sung-Min Hong ,  Bub-chul Jeong

发明人： Jaegeun Yun ,  Sung-Min Hong ,  Bub-chul Jeong

IPC分类号： G06F13/00

CPC分类号： G06F13/1657

摘要： A system on chip includes a plurality of master devices, a plurality of slave devices that supply data in response to requests of the plurality of master devices and pointer update logic configured to process the requests from the plurality of master devices sequentially in a pipeline manner.

摘要翻译： 片上系统包括多个主设备，响应于多个主设备的请求提供数据的多个从设备和配置成以流水线方式顺次处理来自多个主设备的请求的指针更新逻辑。

公开(公告)号：US08819322B2

公开(公告)日：2014-08-26

申请号：US13396155

申请日：2012-02-14

申请人： Jaegeun Yun ,  Sung-Min Hong ,  Bub-chul Jeong

发明人： Jaegeun Yun ,  Sung-Min Hong ,  Bub-chul Jeong

IPC分类号： G06F13/14

CPC分类号： G06F13/1657

摘要： A system on chip includes a plurality of master devices, a plurality of slave devices that supply data in response to requests of the plurality of master devices and pointer update logic configured to process the requests from the plurality of master devices sequentially in a pipeline manner.

摘要翻译： 片上系统包括多个主设备，响应于多个主设备的请求提供数据的多个从设备和配置成以流水线方式顺次处理来自多个主设备的请求的指针更新逻辑。