公开(公告)号：US08519472B2

公开(公告)日：2013-08-27

申请号：US12831728

申请日：2010-07-07

申请人： Jaehun Jeong ,  Ju-Young Lim ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Jae-Joo Shim

发明人： Jaehun Jeong ,  Ju-Young Lim ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Jae-Joo Shim

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11582

摘要： A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures.

摘要翻译： 半导体器件包括堆叠栅结构，其包括多个单元栅极图案和交替层叠在半导体衬底上并沿第一方向延伸的绝缘图案。 有源图案和栅极电介质图案设置在堆叠栅极结构中。 有源图案穿透层叠栅极结构并且在与第一方向相交的第二方向上彼此间隔开，并且栅极电介质图案插入在单元栅极图案和有源图案之间并且延伸到第一方向的上表面和下表面 单元格栅格图案。 有源图案共享堆叠栅极结构中的单元栅极图案。

公开(公告)号：US20110012189A1

公开(公告)日：2011-01-20

申请号：US12831728

申请日：2010-07-07

申请人： Jaehun Jeong ,  Ju-Young Lim ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Jae-Joo Shim

发明人： Jaehun Jeong ,  Ju-Young Lim ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Jae-Joo Shim

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11582

摘要： A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures.

摘要翻译： 半导体器件包括堆叠栅结构，其包括多个单元栅极图案和交替层叠在半导体衬底上并沿第一方向延伸的绝缘图案。 有源图案和栅极电介质图案设置在堆叠栅极结构中。 有源图案穿透层叠栅极结构并且在与第一方向相交的第二方向上彼此间隔开，并且栅极电介质图案插入在单元栅极图案和有源图案之间并且延伸到第一方向的上表面和下表面 单元格栅格图案。 有源图案共享堆叠栅极结构中的单元栅极图案。

公开(公告)号：US20120322252A1

公开(公告)日：2012-12-20

申请号：US13594102

申请日：2012-08-24

申请人： Byoungkeun SON ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

发明人： Byoungkeun SON ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

IPC分类号： H01L21/336

CPC分类号： H01L27/0207 ,  G11C7/18 ,  H01L23/535 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

摘要翻译： 半导体存储器件包括基本上平面的衬底; 垂直于衬底的存储器串，所述存储器串包括多个存储单元; 和多个细长字线，每个字线包括基本上平行于衬底并连接到存储器串的第一部分和相对于衬底基本上倾斜并在衬底上延伸的第二部分，其中多个 字线电连接到设置在存储器串的第一侧的第一导线，并且多个字线的第二组电连接到设置在存储器串的第二侧的第二导电线。

公开(公告)号：US08787082B2

公开(公告)日：2014-07-22

申请号：US13594102

申请日：2012-08-24

申请人： Byoungkeun Son ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

发明人： Byoungkeun Son ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

IPC分类号： G11C16/04

CPC分类号： H01L27/0207 ,  G11C7/18 ,  H01L23/535 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

摘要翻译： 半导体存储器件包括基本上平面的衬底; 垂直于衬底的存储器串，所述存储器串包括多个存储单元; 和多个细长字线，每个字线包括基本上平行于衬底并连接到存储器串的第一部分和相对于衬底基本上倾斜并在衬底上延伸的第二部分，其中多个 字线电连接到设置在存储器串的第一侧的第一导线，并且多个字线的第二组电连接到设置在存储器串的第二侧的第二导电线。

公开(公告)号：US08284601B2

公开(公告)日：2012-10-09

申请号：US12752485

申请日：2010-04-01

申请人： Byoungkeun Son ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

发明人： Byoungkeun Son ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

IPC分类号： G11C16/04

CPC分类号： H01L27/0207 ,  G11C7/18 ,  H01L23/535 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a substantially planar substrate, a memory string vertical to the substrate, the memory string comprising a plurality of storage cells, and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

摘要翻译： 半导体存储器件包括基本上平面的衬底，垂直于衬底的存储器串，存储串包括多个存储单元，以及多个细长字线，每个字线包括基本上平行于衬底的第一部分， 到存储器串和相对于衬底基本上倾斜并在衬底上延伸的第二部分，其中多个字线中的第一组电连接到设置在存储器串的第一侧的第一导电线，以及第二组 多个字线的组电连接到设置在存储器串的第二侧的第二导线。

公开(公告)号：US20100254191A1

公开(公告)日：2010-10-07

申请号：US12752485

申请日：2010-04-01

申请人： Byoungkeun Son ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

发明人： Byoungkeun Son ,  Hansoo Kim ,  Youngsoo An ,  Mingu Kim ,  Jinho Kim ,  Jaehyoung Choi ,  Sukhun Choi ,  Jae-Joo Shim ,  Wonseok Cho ,  Sunil Shim ,  Ju-Young Lim

IPC分类号： G11C16/02 ,  H01L21/3205

CPC分类号： H01L27/0207 ,  G11C7/18 ,  H01L23/535 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

摘要翻译： 半导体存储器件包括基本上平面的衬底; 垂直于衬底的存储器串，所述存储器串包括多个存储单元; 以及多个细长字线，每个字线包括基本上平行于衬底并连接到存储器串的第一部分和相对于衬底基本上倾斜并在衬底上方延伸的第二部分，其中多个 字线电连接到设置在存储器串的第一侧的第一导线，并且多个字线的第二组电连接到设置在存储器串的第二侧的第二导电线。

公开(公告)号：US20100193861A1

公开(公告)日：2010-08-05

申请号：US12694339

申请日：2010-01-27

申请人： Sunil Shim ,  Hansoo Kim ,  Jaehoon Jang ,  Jaehun Jeong

发明人： Sunil Shim ,  Hansoo Kim ,  Jaehoon Jang ,  Jaehun Jeong

IPC分类号： H01L29/78

CPC分类号： H01L27/11551 ,  G11C16/0483 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

摘要： A three-dimensional semiconductor device includes a semiconductor substrate, vertical channel structures arranged on the semiconductor substrate in a matrix, a P-type semiconductor layer disposed at the semiconductor substrate to be in direct with the vertical channel structures, and a common source line disposed at the semiconductor substrate between the vertical channel structures. The common source line may be in contact with the P-type semiconductor layer.

摘要翻译： 三维半导体器件包括：半导体衬底，以矩阵形式布置在半导体衬底上的垂直沟道结构;设置在半导体衬底处以与垂直沟道结构直接相连的P型半导体层;以及布置的公共源极线 在垂直沟道结构之间的半导体衬底处。 公共源极线可以与P型半导体层接触。

公开(公告)号：US09012977B2

公开(公告)日：2015-04-21

申请号：US14154834

申请日：2014-01-14

申请人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Su-Youn Yi ,  Jaehoon Jang ,  Sunghoi Hur

发明人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Su-Youn Yi ,  Jaehoon Jang ,  Sunghoi Hur

IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L27/02 ,  H01L27/115

CPC分类号： H01L27/0207 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

摘要翻译： 提供了一种半导体存储器件。 在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。 第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

公开(公告)号：US20130075807A1

公开(公告)日：2013-03-28

申请号：US13684857

申请日：2012-11-26

申请人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Sunghoi Hur ,  Jaehoon Jang ,  Su-Youn Yi

发明人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Sunghoi Hur ,  Jaehoon Jang ,  Su-Youn Yi

IPC分类号： H01L29/792

CPC分类号： H01L27/0207 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

摘要翻译： 提供了一种半导体存储器件。 在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。 第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

公开(公告)号：US08115259B2

公开(公告)日：2012-02-14

申请号：US12694339

申请日：2010-01-27

申请人： Sunil Shim ,  Hansoo Kim ,  Jaehoon Jang ,  Jaehun Jeong

发明人： Sunil Shim ,  Hansoo Kim ,  Jaehoon Jang ,  Jaehun Jeong

IPC分类号： H01L21/70

CPC分类号： H01L27/11551 ,  G11C16/0483 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

摘要： A three-dimensional semiconductor device includes a semiconductor substrate, vertical channel structures arranged on the semiconductor substrate in a matrix, a P-type semiconductor layer disposed at the semiconductor substrate to be in direct with the vertical channel structures, and a common source line disposed at the semiconductor substrate between the vertical channel structures. The common source line may be in contact with the P-type semiconductor layer.

摘要翻译： 三维半导体器件包括：半导体衬底，以矩阵形式布置在半导体衬底上的垂直沟道结构;设置在半导体衬底处以与垂直沟道结构直接相连的P型半导体层;以及布置的公共源极线 在垂直沟道结构之间的半导体衬底处。 公共源极线可以与P型半导体层接触。