公开(公告)号：US5196652A

公开(公告)日：1993-03-23

申请号：US633923

申请日：1990-12-26

申请人： James C. Mikkelsen, Jr. ,  William Meuli ,  Richard Bruce ,  Jackson Ho

发明人： James C. Mikkelsen, Jr. ,  William Meuli ,  Richard Bruce ,  Jackson Ho

IPC分类号： G09F9/00 ,  G09F9/35 ,  G09F9/40 ,  H01R4/02 ,  H01R4/04 ,  H01R12/52 ,  H05K1/11 ,  H05K1/14 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36

CPC分类号： H05K1/142 ,  G09F9/35 ,  H01R12/52 ,  H05K3/3405 ,  H05K3/36 ,  H01R4/02 ,  H05K1/117 ,  H05K2201/09154 ,  H05K2203/049 ,  H05K3/321 ,  H05K3/328 ,  Y10T29/49149

摘要： A method for electrically connecting planar element substrates (12) to form an array (10) by forming conductive bridges (16) between metal pads (14) located on the surface of array elements (12). These bridges (16) are designed to transmit or receive visual, acoustical or other electromagnetic data and power. The conductive bridges (16) are formed to be nearly coplanar with the planar elements (12) and are made to connect the edges (14b) of pads (14) which are fused to the planar substrate (12). Metal wire (16a), solder (16b-c), a conductive polymer (16d), or a suspension of conductive particles in paste (16e) are used to bridge and electrically connect the pads (14) located on the array elements (12). The bridges (16) have a low profile, occupy a very small area and reduce the need for highly accurate alignment of adjacent substrates (12) within the tiled array (10) before electrical connections are formed. These low profile bridges (16) are especially advantageous in that they allow a protective plastic or similar cover sheet, or a liquid crystal laminate to be surface mounted on the composite array (10) without causing detrimental surface blemishes or ridges. The small area of the bridges (16) greatly reduces the non-transmitting area of the visual display. The bridges (16), being substantially narrower than the pads (14) which they connect, are more likely to connect the intended pads (14) and less likely to "short" pads (14) which are not in accurate alignment.

公开(公告)号：US4306916A

公开(公告)日：1981-12-22

申请号：US77383

申请日：1979-09-20

申请人： Donald L. Wollesen ,  William Meuli ,  Philip S. Shiota

发明人： Donald L. Wollesen ,  William Meuli ,  Philip S. Shiota

IPC分类号： H01L21/76 ,  H01L21/033 ,  H01L21/266 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/08 ,  H01L29/06 ,  H01L29/78 ,  H01L7/54 ,  B01J17/00 ,  H01L21/265

CPC分类号： H01L21/266 ,  H01L21/033 ,  H01L21/76218 ,  H01L21/823807 ,  Y10S438/965

摘要： A method for fabricating a complementary metal-oxide-silicon (CMOS) integrated circuit device by forming a composite layer of oxide and nitride on the surface of a silicon substrate defined into predetermined areas for the subsequent formation of transistors, masking the substrate to expose preselected areas for P-wells, ion implanting P-type material in the exposed areas to form P-wells so that a relatively high doping level is provided to a greater depth around composite areas within the P-wells areas and a relatively lower doping level is established under the composite layer areas with the P-wells. The ion implantation of P-type material may be accomplished in either a single stage or a two stage procedure.

摘要翻译： 一种用于制造互补金属氧化物 - 硅（CMOS）集成电路器件的方法，其通过在限定到预定区域中的硅衬底的表面上形成氧化物和氮化物的复合层，以便随后形成晶体管，掩蔽衬底以暴露预选 用于P阱的区域，在暴露区域中离子注入P型材料以形成P阱，使得在P阱区域内的复合区域附近提供相对高的掺杂水平，并且相对较低的掺杂水平为 在复合层区域建立了P井。 P型材料的离子注入可以在单阶段或两阶段程序中完成。