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    Modifying Integrated Circuit Designs to Achieve Multiple Operating Frequency Targets
    2.
    发明申请
    Modifying Integrated Circuit Designs to Achieve Multiple Operating Frequency Targets 有权
    改进集成电路设计，实现多个工作频率目标

    公开(公告)号：US20080244473A1

    公开(公告)日：2008-10-02

    申请号：US11693081

    申请日：2007-03-29

    申请人： James C. Parker ,  Vishwas Rao

    发明人： James C. Parker ,  Vishwas Rao

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/08 ,  G06F2217/84

    摘要： A first integrated circuit design with a first maximum operating frequency is modified to achieve a second integrated circuit design with a second maximum operating frequency. The integrated circuit design comprises an arrangement of cells. Each of these cells drives a signal that propagates through a net of other circuit elements to one or more nodes that are limited by respective signal timing constraints. An analytical cost function is assigned to each of the cells. Each analytical cost function comprises a value for its respective cell that is based on one or more speed-related factors indicative of the impact of the respective cell on the first maximum operating frequency of the first integrated circuit design. One or more of the cells are replaced with different cells based on the determined analytical cost functions.

    摘要翻译： 修改了具有第一最大工作频率的第一集成电路设计，以实现具有第二最大工作频率的第二集成电路设计。 集成电路设计包括单元的布置。 这些单元中的每一个驱动通过其它电路元件的网络传播到由相应的信号时序约束限制的一个或多个节点的信号。 分配成本函数分配给每个单元。 每个分析成本函数包括基于指示相应单元对第一集成电路设计的第一最大工作频率的影响的一个或多个速度相关因素的其相应单元的值。 基于确定的分析成本函数，一个或多个单元被不同的单元替换。

    Modifying integrated circuit designs to achieve multiple operating frequency targets
    3.
    发明授权
    Modifying integrated circuit designs to achieve multiple operating frequency targets 有权
    修改集成电路设计以实现多个工作频率目标

    公开(公告)号：US07930674B2

    公开(公告)日：2011-04-19

    申请号：US11693081

    申请日：2007-03-29

    申请人： James C. Parker ,  Vishwas Rao

    发明人： James C. Parker ,  Vishwas Rao

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/08 ,  G06F2217/84

    摘要： A first integrated circuit design with a first maximum operating frequency is modified to achieve a second integrated circuit design with a second maximum operating frequency. The integrated circuit design comprises an arrangement of cells. Each of these cells drives a signal that propagates through a net of other circuit elements to one or more nodes that are limited by respective signal timing constraints. An analytical cost function is assigned to each of the cells. Each analytical cost function comprises a value for its respective cell that is based on one or more speed-related factors indicative of the impact of the respective cell on the first maximum operating frequency of the first integrated circuit design. One or more of the cells are replaced with different cells based on the determined analytical cost functions.

    摘要翻译： 修改了具有第一最大工作频率的第一集成电路设计，以实现具有第二最大工作频率的第二集成电路设计。 集成电路设计包括单元的布置。 这些单元中的每一个驱动通过其它电路元件的网传播到由相应的信号时序约束限制的一个或多个节点的信号。 分配成本函数分配给每个单元。 每个分析成本函数包括基于指示相应单元对第一集成电路设计的第一最大工作频率的影响的一个或多个速度相关因素的其相应单元的值。 基于确定的分析成本函数，一个或多个单元被不同的单元替换。

    SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY
    4.
    发明申请
    SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY 审中-公开
    用于分析和比较采用电压调节的集成电路和集成电路的优化方法的系统，正则化公制

    公开(公告)号：US20130055175A1

    公开(公告)日：2013-02-28

    申请号：US13599549

    申请日：2012-08-30

    申请人： Joseph J. Jamann ,  James C. Parker ,  Vishwas M. Rao

    发明人： Joseph J. Jamann ,  James C. Parker ,  Vishwas M. Rao

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G01R31/31725 ,  G06F1/04 ,  G06F1/26 ,  G06F1/3203 ,  G06F17/5081 ,  H03K19/215

    摘要： Various embodiments of methods of designing an integrated circuit (IC) are provided herein. One embodiment of one such method includes: (1) generating a functional IC design, (2) determining a target clock rate for the functional IC design, (3) generating a netlist from the functional IC design that meets the target clock rate, (4) determining a unitless performance/power quantifier from the netlist, (5) attempting to increase the unitless performance/power quantifier by changing at least one of a speed, an area and a power consumption in at least some noncritical paths in the netlist, wherein the attempting is performed by a processor and (6) generating a layout of the IC from the netlist.

    摘要翻译： 本文提供了设计集成电路（IC）的方法的各种实施例。 一种这样的方法的一个实施例包括：（1）产生功能IC设计，（2）确定功能IC设计的目标时钟速率，（3）从满足目标时钟速率的功能IC设计生成网表（ 4）从网表确定无单位性能/功率量化器，（5）尝试通过改变网表中的至少一些非关键路径中的速度，面积和功率消耗中的至少一个来增加无单位性能/功率量化器， 其中所述尝试由处理器执行，并且（6）从所述网表生成所述IC的布局。

    METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CONTEXT-SENSITIVE AND PROGRESSIVE RULES AND AN APPARATUS EMPLOYING ONE OF THE METHODS
    5.
    发明申请
    METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CONTEXT-SENSITIVE AND PROGRESSIVE RULES AND AN APPARATUS EMPLOYING ONE OF THE METHODS 有权
    用于设计采用语境敏感和进步规则的集成电路的方法和使用方法之一的设备

    公开(公告)号：US20110022996A1

    公开(公告)日：2011-01-27

    申请号：US12510122

    申请日：2009-07-27

    申请人： James C. Parker ,  Vishwas M. Rao ,  Lalita M. Satapathy ,  Todd M. Tope

    发明人： James C. Parker ,  Vishwas M. Rao ,  Lalita M. Satapathy ,  Todd M. Tope

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50

    摘要： Methods of designing an IC and an apparatus are disclosed. In one embodiment, a method includes: (1) creating a functional circuit for a functional block of an IC design, (2) verifying said functional circuit satisfies a rule-set for said IC design, wherein said rule-set is context-based with respect to said design flow, (3) synthesizing a logical circuit based on the functional circuit; (4) verifying the logical circuit satisfies the rule set; (5) implementing a physical layout of the logical circuit; and (6) verifying the physical layout satisfies the rule set, wherein each step of the method is carried out by at least one EDA tool.

    摘要翻译： 公开了设计IC和装置的方法。 在一个实施例中，一种方法包括：（1）创建用于IC设计的功能块的功能电路，（2）验证所述功能电路满足所述IC设计的规则集，其中所述规则集是基于上下文的 相对于所述设计流程，（3）基于功能电路合成逻辑电路; （4）验证逻辑电路满足规则集; （5）实现逻辑电路的物理布局; 和（6）验证物理布局满足规则集，其中该方法的每个步骤由至少一个EDA工具执行。

    Method of emulating an ideal transformer valid from DC to infinite frequency
    7.
    发明授权
    Method of emulating an ideal transformer valid from DC to infinite frequency 失效
    从直流到无限频率仿真理想变压器的方法

    公开(公告)号：US06754616B1

    公开(公告)日：2004-06-22

    申请号：US09494821

    申请日：2000-01-31

    申请人： Bidyut K. Sen ,  James C. Parker ,  Richard L. Wheeler

    发明人： Bidyut K. Sen ,  James C. Parker ,  Richard L. Wheeler

    IPC分类号： G06G762

    CPC分类号： G06F17/5036 ,  H01F19/08

    摘要： A method of simulating the electrical behavior of an ideal transformer. The representation of the ideal transformer is frequency independent and can be used to simulate the behavior of an ideal transformer over the frequency range from DC to infinity. In one embodiment, the ideal transformer is represented as having an input sub-circuit and an output sub-circuit. Each sub-circuit includes a resistor connected in parallel across a current controlled current source. The input current, output current, current sources, and resistances are scaled by a scaling factor representing the turns ratio between the primary and secondary windings of a physical transformer. In the present invention, the current sources are responsible for the current scaling and the resistors are responsible for the impedance scaling. The circuit elements of the representation may be used as the basis for generating a set of input parameters for a circuit emulation program.

    摘要翻译： 一种模拟理想变压器电气特性的方法。 理想变压器的表示是频率无关的，可用于模拟从直流到无限的频率范围内的理想变压器的性能。 在一个实施例中，理想变压器被表示为具有输入子电路和输出子电路。 每个子电路包括在电流控制的电流源上并联连接的电阻器。 输入电流，输出电流，电流源和电阻通过表示物理变压器的初级和次级绕组之间的匝数比的比例因子来缩放。 在本发明中，电流源负责电流缩放，电阻负责阻抗缩放。 该表示的电路元件可以用作生成用于电路仿真程序的一组输入参数的基础。

    Systematic, normalized metric for analyzing and comparing optimization techniques for integrated circuits employing voltage scaling and integrated circuits designed thereby
    8.
    发明授权
    Systematic, normalized metric for analyzing and comparing optimization techniques for integrated circuits employing voltage scaling and integrated circuits designed thereby 失效
    用于分析和比较采用电压缩放的集成电路和由此设计的集成电路的优化技术的系统的归一化度量

    公开(公告)号：US08281266B2

    公开(公告)日：2012-10-02

    申请号：US12365010

    申请日：2009-02-03

    申请人： Joseph J. Jamann ,  James C. Parker ,  Vishwas M. Rao

    发明人： Joseph J. Jamann ,  James C. Parker ,  Vishwas M. Rao

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G01R31/31725 ,  G06F1/04 ,  G06F1/26 ,  G06F1/3203 ,  G06F17/5081 ,  H03K19/215

    摘要： Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional IC design that meets the performance objectives by employing a unitless performance/power quantifier as a metric to gauge a degree of optimization thereof and (6) performing a timing signoff of the layout at the optimization target voltage.

    摘要翻译： 设计集成电路（IC）的方法的各种实施例。 一种这样的方法的一个实施例包括：（1）产生IC的功能设计，（2）确定IC的性能目标，（3）确定IC的优化目标电压，（4）确定IC是否需要电压 缩放以实现优化目标电压下的性能目标，如果是，则采用静态电压缩放或自适应电压缩放，（5）使用优化目标电压从功能IC设计中合成布局，满足 通过采用无单位性能/功率量化器作为衡量其优化程度的度量的性能目标，以及（6）在优化目标电压下执行布局的定时签出。

    Area-efficient power switching cell
    9.
    发明授权
    Area-efficient power switching cell 失效
    区域效率的电力开关电池

    公开(公告)号：US07712066B2

    公开(公告)日：2010-05-04

    申请号：US11322103

    申请日：2005-12-29

    申请人： Martin J. Gasper, Jr. ,  James C. Parker ,  Clayton E. Schneider, Jr.

    发明人： Martin J. Gasper, Jr. ,  James C. Parker ,  Clayton E. Schneider, Jr.

    IPC分类号： G06F9/45 ,  G06F17/50 ,  G06F7/38 ,  H03K19/173

    CPC分类号： H03K17/687

    摘要： A power switching circuit is provided for use in an integrated circuit including at least a first voltage rail and a second voltage rail. The power switching circuit includes at least one MOS device having a first source/drain adapted for connection to the first voltage rail, a second source/drain adapted for connection to the second voltage rail, and a gate adapted for receiving a control signal. The MOS device selectively connects the first voltage rail to the second voltage rail in response to the control signal. The first and second voltage rails form a grid overlying the power switching circuit, the first and second voltage rails being formed in different planes relative to one another. The connection between the power switching circuit and the first voltage rail is made at an interface between the first and voltage rails.

    摘要翻译： 电源开关电路用于至少包括第一电压轨和第二电压轨的集成电路中。 功率开关电路包括至少一个MOS器件，其具有适于连接到第一电压轨的第一源极/漏极，适于连接到第二电压轨的第二源/漏极和适于接收控制信号的栅极。 MOS器件响应于控制信号选择性地将第一电压轨连接到第二电压轨。 第一和第二电压轨形成覆盖功率开关电路的电网，第一和第二电压轨相对于彼此形成在不同的平面中。 电源开关电路和第一电压轨之间的连接在第一和电压轨之间的接口处形成。

    Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method
    10.
    发明授权
    Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method 失效
    使用分层分层设计流程设计集成电路的方法和采用该方法的装置

    公开(公告)号：US08539419B2

    公开(公告)日：2013-09-17

    申请号：US13421710

    申请日：2012-03-15

    申请人： Vishwas M. Rao ,  James C. Parker

    发明人： Vishwas M. Rao ,  James C. Parker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5045 ,  G06F2217/84

    摘要： Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, the method includes: (1) receiving timing and physical constraints for an IC design at an apparatus, (2) establishing a hierarchical design flow for providing an implementation of the IC design employing the apparatus and (3) partitioning the hierarchical design flow into a late design flow portion and an early design flow portion employing the apparatus, wherein the late design flow portion is substantially the same for different design flow methodologies.

    摘要翻译： 公开了设计IC和分层设计流发生器的方法。 在一个实施例中，该方法包括：（1）在设备处接收用于IC设计的定时和物理约束，（2）建立分层设计流程，以提供采用该设备的IC设计的实现，以及（3） 设计流入后期设计流程部分和采用该装置的早期设计流程部分，其中后期设计流程部分对于不同的设计流程方法基本相同。