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    Method for controlling the operation of a computer implemented apparatus to selectively execute instructions of different bit lengths
    2.
    发明授权
    Method for controlling the operation of a computer implemented apparatus to selectively execute instructions of different bit lengths 失效
    用于控制计算机实现的装置的操作以选择性地执行不同位长的指令的方法

    公开(公告)号：US5511174A

    公开(公告)日：1996-04-23

    申请号：US286662

    申请日：1994-08-05

    申请人： Gary D. Hicok ,  Thomas Alexander ,  Yong J. Lim ,  Yongmin Kim

    发明人： Gary D. Hicok ,  Thomas Alexander ,  Yong J. Lim ,  Yongmin Kim

    IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F12/00

    CPC分类号： G06F9/321 ,  G06F9/30149

    摘要： A method for selectively controlling the operation of a computer system so that the computer system is selectively caused to execute instructions of a first predetermined bit length or instructions of a second predetermined bit length. The method comprises the preliminary steps of storing instruction data in a set of EVEN instruction storage locations; storing instruction data in a set of ODD instruction locations; establishing an EVEN execution pointer; and establishing an ODD execution pointer. At a first given time, either the EVEN execution pointer is incremented by a predetermined COUNT or the ODD execution pointer is incremented by the predetermined COUNT; but both pointers are not simultaneously incremented by the COUNT. The method causes an instruction to be executed, which instruction was stored entirely in either an EVEN instruction location or entirely in an ODD instruction location. At a second given time, both the EVEN instruction pointer and the ODD instruction pointer are incremented by the predetermined COUNT, thereby causing an instruction to be executed, which instruction constitutes a combination of instruction data from an EVEN instruction storage location and instruction data from an ODD instruction storage location.

    摘要翻译： 一种用于选择性地控制计算机系统的操作的方法，使得选择性地使计算机系统执行第一预定位长度的指令或第二预定位长度的指令。 该方法包括将指令数据存储在一组EVEN指令存储位置中的预备步骤; 将指令数据存储在一组ODD指令位置中; 建立一个EVEN执行指针; 并建立一个ODD执行指针。 在第一给定时间，将EVEN执行指针递增预定的COUNT，或者ODD执行指针递增预定的COUNT; 但是两个指针都不会同时递增COUNT。 该方法导致执行指令，哪个指令完全存储在EVEN指令位置或完全存储在ODD指令位置。 在第二给定时间，EVEN指令指针和ODD指令指针都被增加预定的COUNT，从而使指令被执行，该指令构成来自EVEN指令存储位置的指令数据和来自 ODD指令存储位置。

    Caching FIFO and method therefor
    3.
    发明授权
    Caching FIFO and method therefor 失效
    缓存FIFO及其方法

    公开(公告)号：US5557733A

    公开(公告)日：1996-09-17

    申请号：US42306

    申请日：1993-04-02

    申请人： Gary D. Hicok ,  Judson A. Lehman

    发明人： Gary D. Hicok ,  Judson A. Lehman

    IPC分类号： G06F5/06 ,  G06F12/02 ,  G06F15/00

    CPC分类号： G06F5/065 ,  G06F12/0215

    摘要： A memory subsystem for use between a CPU and a graphics controller in a typical small computer system has a cache interface for the CPU and a FIFO interface for the graphics controller. This configuration optimizes the data transfers for both the CPU and the graphics controller, and allows both to operate in a manner generally asynchronous to each other. This caching FIFO provides enhanced performance by matching the interface to the unique data requirements of the devices accessing the data within the caching FIFO. For the CPU, the caching FIFO appears as a normal data cache. For the graphics controller, the caching FIFO appears as a normal dual port FIFO, which optimizes the highly sequential data transfers characteristic of graphics controllers. The simple design of the caching FIFO provides maximum performance for a minimum of gates, making the circuit well-suited to efficient implementation in silicon.

    摘要翻译： 在典型的小型计算机系统中用于CPU和图形控制器的存储器子系统具有用于CPU的高速缓存接口和用于图形控制器的FIFO接口。 该配置优化了CPU和图形控制器的数据传输，并且允许两者以大体上彼此异步的方式操作。 该缓存FIFO通过将接口与访问缓存FIFO中的数据的设备的唯一数据需求相匹配来提供增强的性能。 对于CPU，缓存FIFO显示为普通数据缓存。 对于图形控制器，缓存FIFO显示为普通双端口FIFO，可优化图形控制器的高度顺序数据传输特性。 缓存FIFO的简单设计为最小的门提供了最大的性能，使得该电路非常适合在硅中有效实现。

    Power management system for a computer
    4.
    发明授权
    Power management system for a computer 失效
    电脑电源管理系统

    公开(公告)号：US5958055A

    公开(公告)日：1999-09-28

    申请号：US717478

    申请日：1996-09-20

    申请人： David R. Evoy ,  Gary D. Hicok ,  Laura E. Simmons

    发明人： David R. Evoy ,  Gary D. Hicok ,  Laura E. Simmons

    IPC分类号： G06F1/32 ,  G06F11/00

    CPC分类号： G06F1/3209 ,  G06F11/004

    摘要： An off-hook state of a telephone associated with a computer is used in order to disable the power management unit of the computer to prevent premature power shutdown while the telephone is being used. A power-managed computer system includes a bus system, and a central processing unit coupled to the bus system. The central processing unit has a normal power mode and a power saving mode. A telephony interface coupled to the bus system has a port for coupling to a telephone system network. A power management unit is also coupled to the bus system and is responsive to bus system activity and to indicia of telephony interface activity. The power management unit causes the central processing unit to be in a power saving mode when both bus system activity and telephony interface activity are less than a predetermined level of activity. Additionally, the power management unit maintains the central processing unit in a power mode greater than the power saving mode when either the bus system activity or the telephony interface activity is greater than the predetermined level of activity. An off-hook signal is directly sampled from the modem and provided to activity detection logic within the power management unit. Alternatively, modem interface logic interprets any number of signals provided by the modem to deliver an off-hook signal to the power management unit. Alternatively, telephone interface software includes an off-hook identifier that records the off-hook state of the telephone and an enablement/disablement register in the power management unit is either set or reset. System or user activity is also emulated in order to indicate to the power management unit that activity is occurring within the computer.

    摘要翻译： 使用与计算机相关联的电话机的摘机状态，以便禁用计算机的电源管理单元以防止在使用电话时过早停电。 功率管理的计算机系统包括总线系统和耦合到总线系统的中央处理单元。 中央处理单元具有正常功率模式和省电模式。 耦合到总线系统的电话接口具有用于耦合到电话系统网络的端口。 电力管理单元还耦合到总线系统，并响应于总线系统活动和电话接口活动的标记。 当总线系统活动和电话接口活动都小于预定活动水平时，电源管理单元使得中央处理单元处于省电模式。 此外，当总线系统活动或电话接口活动大于预定活动水平时，电力管理单元将中央处理单元维持在大于省电模式的功率模式中。 摘机信号从调制解调器直接采样并提供给电源管理单元内的活动检测逻辑。 或者，调制解调器接口逻辑解释由调制解调器提供的任何数量的信号以将摘机信号传送到电力管理单元。 或者，电话接口软件包括记录电话的摘机状态的摘机标识符，并且电源管理单元中的启用/禁用寄存器被设置或复位。 系统或用户活动也被仿真，以向电力管理单元指示在计算机内发生的活动。

    Input/output (I/O) holdoff mechanism for use in a system where I/O device inputs are fed through a latency introducing bus
    5.
    发明授权
    Input/output (I/O) holdoff mechanism for use in a system where I/O device inputs are fed through a latency introducing bus 失效
    输入/输出（I / O）抑制机制，用于通过延迟引入总线馈送I / O设备输入的系统

    公开(公告)号：US5664213A

    公开(公告)日：1997-09-02

    申请号：US504936

    申请日：1995-07-20

    申请人： James C. Steele ,  Gary D. Hicok ,  David R. Evoy ,  Gary A. Walker ,  Joseph A. Thomsen ,  Lonnie C. Goff

    发明人： James C. Steele ,  Gary D. Hicok ,  David R. Evoy ,  Gary A. Walker ,  Joseph A. Thomsen ,  Lonnie C. Goff

    IPC分类号： G06F13/32 ,  G06F13/38 ,  G06F13/42 ,  G06F13/00

    CPC分类号： G06F13/32 ,  G06F13/385 ,  G06F13/423

    摘要： An I/O holdoff mechanism is used to compensate for I/O device inputs being fed through a latency introducing bus. A system includes one or more I/O devices connected through a serial bus to a controller device. Each I/O device includes at least one request pin which is connected to a peripheral device. A serializer in the I/O device responds to a voltage transition occurring on any request pin of the I/O device by forwarding, in a packet over the serial bus, an indicator. The indicator indicates a current voltage on the request pin of the I/O device on which the voltage transition occurred. The controller device includes a deserializer and a bus controller. The deserializer receives the first packet and outputs a signal which indicates a current value for the voltage on the indicated request pin. The deserializer includes a busy output which indicates when the deserializer is busy and when the deserializer is idle. The bus controller responds to a request from a host system for a current value on a first request pin of the I/O device by forwarding to the host system a current value for a voltage on the indicated request pin, as indicated by the deserializer, when the deserializer is not busy. When the deserializer is busy, the bus controller responds to the request from the host system for the current value on the first request pin of the I/O device by waiting for the deserializer to become idle. Upon the deserializer becoming idle, the bus controller forwards to the host system the current value for the voltage on the indicated request pin.

    摘要翻译： 使用I / O缓存机制来补偿通过延迟引入总线馈送的I / O设备输入。 系统包括通过串行总线连接到控制器设备的一个或多个I / O设备。 每个I / O设备包括至少一个连接到外围设备的请求引脚。 I / O设备中的串行器响应I / O设备的任何请求引脚上发生的电压转换，通过串行总线上的数据包转发一个指示器。 该指示灯表示发生电压转换的I / O设备的请求引脚上的当前电压。 控制器设备包括解串器和总线控制器。 解串器接收第一个数据包，并输出指示指示的请求引脚上的电压的当前值的信号。 解串器包括一个忙输出，指示解串器何时正在忙和解串器空闲时。 总线控制器通过向主机系统转发指示的请求引脚上的电压的当前值，如由解串器指示的那样，响应来自主机系统对于I / O设备的第一请求引脚上的当前值的请求， 当解串器不忙时。 当解串器处于忙时，总线控制器通过等待解串器空闲来响应来自主机系统对I / O设备的第一个请求引脚上当前值的请求。 在解串器变为空闲状态时，总线控制器向主机系统转发指定请求引脚上的电压的当前值。

    Encoding assertion and de-assertion of interrupt requests and DMA requests in a serial bus I/O system
    6.
    发明授权
    Encoding assertion and de-assertion of interrupt requests and DMA requests in a serial bus I/O system 失效
    在串行总线I / O系统中编码断言和解除中断请求和DMA请求

    公开(公告)号：US5634069A

    公开(公告)日：1997-05-27

    申请号：US503795

    申请日：1995-07-18

    申请人： Gary D. Hicok ,  David R. Evoy ,  Gary A. Walker ,  Joseph A. Thomsen ,  Lonnie C. Goff ,  Bruce E. Cairns

    发明人： Gary D. Hicok ,  David R. Evoy ,  Gary A. Walker ,  Joseph A. Thomsen ,  Lonnie C. Goff ,  Bruce E. Cairns

    IPC分类号： G06F13/32 ,  G06F13/38 ,  G06F13/42 ,  G06F13/14

    CPC分类号： G06F13/32 ,  G06F13/385 ,  G06F13/423

    摘要： A computing system encodes and emulates requests signals, such as DMA requests or interrupt requests. A first peripheral device is connected to a first request pin of a first input/output (I/O) device. When the first peripheral device asserts a first request signal on the first request pin, a serializer within the first I/O device generates a first packet. The serializer forwards the first packet to a serial out port of the first I/O device. The first packet identifies the type of request and the direction of the edge transition. The serial out port forwards the first packet to a serial in port of a controller device. Upon the serial in port receiving the first packet, an unserializer within the controller device asserts an emulated first request signal, the emulated first request signal being coupled to a first request controller within the controller device. When the first peripheral device de-asserts the first request signal on the first request pin of the first I/O device, the serializer generates a second packet. The second packet identifies the type of request and the direction of the edge transition. The serializer forwards the second packet to the serial out port of the first I/O device. The serial out port of the first I/O device forwards the second packet to the serial in port of the controller device. Upon the serial in port receiving the second packet, the unserializer within the request controller de-asserts the emulated first request signal. When the first peripheral device pulses the first request signal by quickly de-asserting and asserting the first request signal in quick succession, the second packet is sent, but not the first packet.

    摘要翻译： 计算系统对DMA请求或中断请求等请求信号进行编码和仿真。 第一外围设备连接到第一输入/输出（I / O）设备的第一请求引脚。 当第一外围设备在第一请求引脚上断言第一请求信号时，第一I / O设备内的串行器产生第一分组。 串行器将第一个数据包转发到第一个I / O设备的串行输出端口。 第一个数据包标识请求的类型和边沿转换的方向。 串行端口将第一个数据包转发到控制器设备的串行端口。 在串行端口接收第一分组时，控制器设备内的非串行化器断言模拟的第一请求信号，仿真的第一请求信号耦合到控制器设备内的第一请求控制器。 当第一外围设备在第一I / O设备的第一请求引脚上取消断言第一请求信号时，串行器产生第二分组。 第二个分组标识请求的类型和边缘转换的方向。 串行器将第二个数据包转发到第一个I / O设备的串行输出端口。 第一个I / O设备的串行端口将第二个数据包转发到控制器设备的串口。 在串行端口接收第二分组时，请求控制器内的非串行化器取消断言仿真的第一请求信号。 当第一外围设备通过快速地取消断言和断言第一请求信号来脉冲第一请求信号时，发送第二个分组，而不是第一个分组。

    Variable band size compositing buffer method and apparatus
    9.
    发明授权
    Variable band size compositing buffer method and apparatus 失效
    可变带宽合成缓冲方法及装置

    公开(公告)号：US5835104A

    公开(公告)日：1998-11-10

    申请号：US841360

    申请日：1997-04-23

    申请人： Gary D. Hicok ,  Jeffery M. Michelsen

    发明人： Gary D. Hicok ,  Jeffery M. Michelsen

    IPC分类号： G06F3/14 ,  G09G5/02 ,  G09G5/36 ,  G09G5/39 ,  G09G5/397 ,  G09G5/42

    CPC分类号： G09G5/363 ,  G09G3/003 ,  G09G5/397 ,  G09G5/42 ,  G06F3/14 ,  G09G2310/04 ,  G09G2340/02 ,  G09G2360/02 ,  G09G5/022

    摘要： A compositing buffer having an adjustable size and configuration reduces complexity and size of a multimedia processor integrated circuit. The compositing buffer may be optimized for lower resolutions, thus reducing its overall size and complexity, while still providing support for higher resolutions which may be required to support a particular standard. A pixel mapping logic receives data indicating the number of lines per band and number of pixels per line, as well as color depth (or any two of these data) and correctly maps compositing RAM bank access requests to the correct pixel location. In a second embodiment of the present invention, the variable band size of the compositing buffer may allow for an external memory to be used for a compositing buffer, for example, a portion of the display memory (frame buffer). While such an embodiment may reduce overall bandwidth, the associated cost reduction may make such an apparatus appealing for low cost applications. Band size may be adjusted depending upon pixel resolution and depth. In a third embodiment of the present invention, band size may be varied within a frame depending upon the number of layers or the complexity of each image portion. Simple portions of an image, have few layers, may be rendered using wide bands, whereas complex areas may be rendered in narrower bands.

    摘要翻译： 具有可调节尺寸和配置的合成缓冲器降低了多媒体处理器集成电路的复杂度和尺寸。 合成缓冲区可以针对较低分辨率进行优化，从而降低其总体大小和复杂性，同时仍然支持可能需要支持特定标准的更高分辨率。 像素映射逻辑接收指示每行的行数和每行像素数的数据以及颜色深度（或这些数据中的任何两个），并将合并的RAM存储体访问请求正确地映射到正确的像素位置。 在本发明的第二实施例中，合成缓冲器的可变带宽可以允许将外部存储器用于合成缓冲器，例如显示存储器的一部分（帧缓冲器）。 虽然这样的实施例可以减少总体带宽，但是相关联的成本降低可能​​使得这种设备吸引低成本应用。 可以根据像素分辨率和深度来调节乐队的大小。 在本发明的第三实施例中，根据层的数量或每个图像部分的复杂度，可以在一个帧内改变带宽。 图像的简单部分，具有几层，可以使用宽带渲染，而复杂区域可以在较窄的带中呈现。

    Method and apparatus for performing network processing functions
    10.
    发明授权
    Method and apparatus for performing network processing functions 有权
    执行网络处理功能的方法和装置

    公开(公告)号：US08094670B1

    公开(公告)日：2012-01-10

    申请号：US11949734

    申请日：2007-12-03

    申请人： Robert A. Alfieri ,  Gary D. Hicok ,  Paul J. Sidenblad ,  Mark A. Parris

    发明人： Robert A. Alfieri ,  Gary D. Hicok ,  Paul J. Sidenblad ,  Mark A. Parris

    IPC分类号： H04L12/54

    CPC分类号： H04L45/00 ,  H04L49/3009

    摘要： A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.

    摘要翻译： 一种将互联网协议（IP）路由器的功能集成到驻留在主计算机芯片组中的网络处理单元（NPU）的新型网络架构，使得主计算机的资源被感知为单独的网络设备。 即使在一个实施例中它共享相同的芯片，NPU在逻辑上与主计算机分离。