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1.发明授权Control of high-k gate dielectric film composition profile for property optimization 有权控制高k栅极电介质膜组成轮廓的性能优化公开(公告)号：US07071519B2
公开(公告)日：2006-07-04
申请号：US10338310
申请日：2003-01-08
IPC分类号： H01L29/94
CPC分类号： H01L21/02271 , H01L21/28194 , H01L21/3142 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/78
摘要： Methods and systems are disclosed that facilitate formation of dielectric layers having a particular composition profile by forming the dielectric layer as a number of sub-layers. The sub-layers are thin enough so that specific relative compositions can be achieved for each layer and, therefore, the sub-layers collectively yield a dielectric layer with a particular profile. The formation of individual sub layers is accomplished by controlling one or more processing parameters for a chemical vapor deposition process that affect relative compositions. Some processing parameters that can be employed include wafer temperature, pressure, and precursor flow rate.
摘要翻译： 公开了通过将介电层形成多个子层来促进形成具有特定组成分布的电介质层的方法和系统。 子层足够薄，使得可以为每个层实现特定的相对组成，因此，子层共同产生具有特定轮廓的介电层。 单个子层的形成通过控制影响相对组成的化学气相沉积工艺的一个或多个处理参数来实现。 可采用的一些加工参数包括晶片温度，压力和前体流速。
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公开(公告)号：US06828200B2
公开(公告)日：2004-12-07
申请号：US10336441
申请日：2003-01-03
IPC分类号： H01L21336
CPC分类号： H01L21/022 , H01L21/02148 , H01L21/02266 , H01L21/02271 , H01L21/02329 , H01L21/02337 , H01L21/0234 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3144 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention forms a nitrided dielectric layer without substantial harm to a semiconductor layer on which the dielectric layer is formed. The invention employs a multi-stage process in which dielectric sub-layers are individually nitrided before formation of a next dielectric sub-layer. The net result is a nitrided multi-layered dielectric layer comprised of a plurality of dielectric sub-layers wherein the sub-layers have been individually deposited and incorporated with nitrogen.
摘要翻译： 本发明形成氮化电介质层，而对形成介电层的半导体层没有实质的损害。 本发明采用多级工艺，其中在形成下一个电介质子层之前，将电介质子层单独氮化。 最终结果是由多个电介质子层组成的氮化多层电介质层，其中子层已经被单独沉积并与氮结合。
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公开(公告)号：US06750126B1
公开(公告)日：2004-06-15
申请号：US10338276
申请日：2003-01-08
IPC分类号： H01L213205
CPC分类号： H01L21/28202 , H01L21/28035 , H01L21/28194 , H01L21/314 , H01L21/3143 , H01L21/31645 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6659
摘要： Methods are disclosed for fabricating transistor gate structures and high-k dielectric layers therefor by sputter deposition, in which nitridation and/or oxidation or other adverse reaction of the semiconductor material is reduced or minimized by reducing the bombardment of the semiconductor body by positively charged reactive ions such as oxygen ions or nitrogen ions during the sputter deposition process. The sputtering operation may be a two-step process in which ionic bombardment of the semiconductor material is minimized in an initial deposition step to form a first layer portion covering the semiconductor body, and the second step completes the desired high-k dielectric layer. Mitigation of unwanted nitridation and/or oxidation or other adverse reaction is achieved through one, some, or all of high sputtering deposition pressure, repulsive wafer biasing, increased wafer-plasma spacing, low partial pressures for reactant gases, and low sputtering powers or power densities.
摘要翻译： 公开了用于通过溅射沉积来制造晶体管栅极结构和高k电介质层的方法，其中半导体材料的氮化和/或氧化或其它不利反应被减小或最小化，通过减少半导体主体的带正电荷的反应 离子如氧离子或氮离子在溅射沉积过程中。 溅射操作可以是在初始沉积步骤中使半导体材料的离子轰击最小化以形成覆盖半导体本体的第一层部分的两步法，并且第二步骤完成所需的高k电介质层。 通过高溅射沉积压力，排斥晶片偏置，增加的晶片 - 等离子体间隔，反应气体的低分压以及低溅射功率或功率的一种，一些或全部来实现减少不希望的氮化和/或氧化或其它不利反应 密度
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公开(公告)号：US07842567B2
公开(公告)日：2010-11-30
申请号：US12271080
申请日：2008-11-14
IPC分类号： H01L21/00
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966
摘要： Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.
摘要翻译： 同时形成具有各自功函数的不同金属栅极晶体管。 在一个实例中，在半导体衬底上形成具有较低功函数的金属碳化物。 然后在第二区域中将氧和/或氮添加到金属碳化物中以在第二区域中建立第二功函数，其中金属碳化物本身在第一区域中建立第一功函数。 然后在第一区域中形成一个或多个第一金属栅极晶体管类型，并且在第二区域中形成一个或多个第二金属栅极晶体管类型。
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5.发明授权Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials 有权具有NMOS高k电介质的半导体CMOS器件和方法存在于芯区中，可减轻介电材料的损坏公开(公告)号：US07642146B2
公开(公告)日：2010-01-05
申请号：US11620447
申请日：2007-01-05
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842 , Y10S438/981
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.
摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成I / O电介质层。 从器件的芯区域去除（508）I / O电介质层。 在芯区域（510）中形成芯介质层。 屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。 从核心NMOS器件（514）去除芯介质层。 在核心和I / O区域上形成高k电介质层（514）。 然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。
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6.发明授权Method to maximize nitrogen concentration at the top surface of gate dielectrics 有权最大化栅极电介质顶表面的氮浓度的方法公开(公告)号：US08198184B2
公开(公告)日：2012-06-12
申请号：US12570620
申请日：2009-09-30
IPC分类号： H01L29/78 , H01L21/336 , H01L21/314
CPC分类号： H01L21/28202 , H01L21/3145 , H01L21/3185 , H01L29/4916 , H01L29/518 , H01L29/7833
摘要： An integrated circuit having a gate dielectric layer (414, 614, 814) having an improved nitrogen profile and a method of fabrication. The gate dielectric layer is a graded layer with a significantly higher nitrogen concentration at the electrode surface than near the substrate surface. An amorphous silicon layer (406) may be deposited prior to nitridation to retain the nitrogen concentration at the top surface (416). Alternatively, a thin silicon nitride layer (610) may be deposited after anneal or a wet nitridation process may be performed.
摘要翻译： 一种具有具有改进的氮分布的栅介电层（414,614,814）和一种制造方法的集成电路。 栅极电介质层是在电极表面处的氮浓度显着高于衬底表面附近的梯度层。 可以在氮化之前沉积非晶硅层（406）以将氮浓度保持在顶表面（416）。 或者，可以在退火之后沉积薄氮化硅层（610），或者可以执行湿式氮化处理。
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公开(公告)号：US07470577B2
公开(公告)日：2008-12-30
申请号：US11204235
申请日：2005-08-15
IPC分类号： H01L21/00
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966
摘要： Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.
摘要翻译： 同时形成具有各自功函数的不同金属栅极晶体管。 在一个实例中，在半导体衬底上形成具有较低功函数的金属碳化物。 然后在第二区域中将氧和/或氮添加到金属碳化物中以在第二区域中建立第二功函数，其中金属碳化物本身在第一区域中建立第一功函数。 然后在第一区域中形成一个或多个第一金属栅极晶体管类型，并且在第二区域中形成一个或多个第二金属栅极晶体管类型。
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8.发明申请公开(公告)号：US20080157228A1
公开(公告)日：2008-07-03
申请号：US11618650
申请日：2006-12-29
CPC分类号： H01L21/28079 , H01L21/823842 , H01L21/823857 , H01L29/495
摘要： Exemplary embodiments provide structures and fabrication methods for dual work function metal gate electrodes. The work function value of a metal gate electrode can be increased and/or decreased by disposing various electronegative species and/or electropositive species at the metal/dielectric interface to control interface dipoles. In an exemplary embodiment, various electronegative species can be disposed at the metal/dielectric interface to increase the work function value of the metal, which can be used for a PMOS metal gate electrode in a dual work function gated device. Various electropositive species can be disposed at the metal/dielectric interface to decrease the work function value of the metal, which can be used for an NMOS metal gate electrode in the dual work function gated device.
摘要翻译： 示例性实施例提供了用于双功能金属栅电极的结构和制造方法。 通过在金属/电介质界面处设置各种电负性物质和/或正电性物质来控制界面偶极子，可以增加和/或降低金属栅电极的功函数值。 在示例性实施例中，各种电负性物质可以设置在金属/电介质界面处以增加金属的功函数值，其可用于双功能门控器件中的PMOS金属栅电极。 可以在金属/电介质界面处设置各种正电性物质，以降低金属的功函数值，这可以用于双功能门控器件中的NMOS金属栅电极。
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9.发明授权Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials 有权具有NMOS高k电介质的半导体CMOS器件和方法存在于芯区中，可减轻介电材料的损坏公开(公告)号：US07176076B2
公开(公告)日：2007-02-13
申请号：US11118843
申请日：2005-04-29
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842 , Y10S438/981
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.
摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成I / O电介质层。 从器件的芯区域去除（508）I / O电介质层。 在芯区域（510）中形成芯介质层。 屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。 从核心NMOS器件（514）去除芯介质层。 在核心和I / O区域上形成高k电介质层（514）。 然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。
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公开(公告)号：US07601577B2
公开(公告)日：2009-10-13
申请号：US11870631
申请日：2007-10-11
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823842
摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.
摘要翻译： 公开了具有不同功函数的金属栅极晶体管。 在一个示例中，第一金属是“中间间隙”金属，分别在第一和第二区域中被第二和第三金属操纵，以在不同区域中沿相反方向移动第一金属的功函数。 在不同区域中产生的功函数对应于将要形成的不同类型的晶体管。
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