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1.发明授权Control of high-k gate dielectric film composition profile for property optimization 有权控制高k栅极电介质膜组成轮廓的性能优化公开(公告)号：US07071519B2
公开(公告)日：2006-07-04
申请号：US10338310
申请日：2003-01-08
IPC分类号： H01L29/94
CPC分类号： H01L21/02271 , H01L21/28194 , H01L21/3142 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/78
摘要： Methods and systems are disclosed that facilitate formation of dielectric layers having a particular composition profile by forming the dielectric layer as a number of sub-layers. The sub-layers are thin enough so that specific relative compositions can be achieved for each layer and, therefore, the sub-layers collectively yield a dielectric layer with a particular profile. The formation of individual sub layers is accomplished by controlling one or more processing parameters for a chemical vapor deposition process that affect relative compositions. Some processing parameters that can be employed include wafer temperature, pressure, and precursor flow rate.
摘要翻译： 公开了通过将介电层形成多个子层来促进形成具有特定组成分布的电介质层的方法和系统。 子层足够薄，使得可以为每个层实现特定的相对组成，因此，子层共同产生具有特定轮廓的介电层。 单个子层的形成通过控制影响相对组成的化学气相沉积工艺的一个或多个处理参数来实现。 可采用的一些加工参数包括晶片温度，压力和前体流速。
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公开(公告)号：US06750126B1
公开(公告)日：2004-06-15
申请号：US10338276
申请日：2003-01-08
IPC分类号： H01L213205
CPC分类号： H01L21/28202 , H01L21/28035 , H01L21/28194 , H01L21/314 , H01L21/3143 , H01L21/31645 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6659
摘要： Methods are disclosed for fabricating transistor gate structures and high-k dielectric layers therefor by sputter deposition, in which nitridation and/or oxidation or other adverse reaction of the semiconductor material is reduced or minimized by reducing the bombardment of the semiconductor body by positively charged reactive ions such as oxygen ions or nitrogen ions during the sputter deposition process. The sputtering operation may be a two-step process in which ionic bombardment of the semiconductor material is minimized in an initial deposition step to form a first layer portion covering the semiconductor body, and the second step completes the desired high-k dielectric layer. Mitigation of unwanted nitridation and/or oxidation or other adverse reaction is achieved through one, some, or all of high sputtering deposition pressure, repulsive wafer biasing, increased wafer-plasma spacing, low partial pressures for reactant gases, and low sputtering powers or power densities.
摘要翻译： 公开了用于通过溅射沉积来制造晶体管栅极结构和高k电介质层的方法，其中半导体材料的氮化和/或氧化或其它不利反应被减小或最小化，通过减少半导体主体的带正电荷的反应 离子如氧离子或氮离子在溅射沉积过程中。 溅射操作可以是在初始沉积步骤中使半导体材料的离子轰击最小化以形成覆盖半导体本体的第一层部分的两步法，并且第二步骤完成所需的高k电介质层。 通过高溅射沉积压力，排斥晶片偏置，增加的晶片 - 等离子体间隔，反应气体的低分压以及低溅射功率或功率的一种，一些或全部来实现减少不希望的氮化和/或氧化或其它不利反应 密度
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公开(公告)号：US07601577B2
公开(公告)日：2009-10-13
申请号：US11870631
申请日：2007-10-11
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823842
摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.
摘要翻译： 公开了具有不同功函数的金属栅极晶体管。 在一个示例中，第一金属是“中间间隙”金属，分别在第一和第二区域中被第二和第三金属操纵，以在不同区域中沿相反方向移动第一金属的功函数。 在不同区域中产生的功函数对应于将要形成的不同类型的晶体管。
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公开(公告)号：US07291527B2
公开(公告)日：2007-11-06
申请号：US11220451
申请日：2005-09-07
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823842
摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.
摘要翻译： 公开了具有不同功函数的金属栅极晶体管。 在一个示例中，第一金属是“中间间隙”金属，分别在第一和第二区域中被第二和第三金属操纵，以在不同区域中沿相反方向移动第一金属的功函数。 在不同区域中产生的功函数对应于将要形成的不同类型的晶体管。
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公开(公告)号：US07601578B2
公开(公告)日：2009-10-13
申请号：US11924132
申请日：2007-10-25
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/02318 , C23C16/56 , H01L21/02323 , H01L21/28185 , H01L21/28194 , H01L21/3143 , H01L21/31608 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/318 , H01L29/518 , H01L29/78
摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
摘要翻译： 一种改善高卡门电介质膜（104）性能的方法。 对高卡帕膜（104）进行两步退火处理。 第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。 第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。
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6.发明授权Semiconductor device having multiple work functions and method of manufacture therefor 有权具有多种功能的半导体装置及其制造方法公开(公告)号：US07226826B2
公开(公告)日：2007-06-05
申请号：US10826516
申请日：2004-04-16
IPC分类号： H01L21/8238
CPC分类号： H01L21/321 , H01L21/28079 , H01L21/823835 , H01L21/823842
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a metal gate electrode (135) having a work function, and a second transistor (160) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (160) has a plasma altered metal gate electrode (175) having a different work function.
摘要翻译： 本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。 半导体器件（100）以及其他可能的元件包括位于半导体衬底（110）上方的第一晶体管（120），其中第一晶体管（120）具有具有功函数的金属栅电极（135） 第二晶体管（160）位于半导体衬底（110）上并且靠近第一晶体管（120），其中第二晶体管（160）具有具有不同功函数的等离子体改变的金属栅电极（175）。
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公开(公告)号：US07015088B2
公开(公告)日：2006-03-21
申请号：US10335560
申请日：2002-12-31
IPC分类号： H01L21/00 , H01L21/8242
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/517 , H01L29/518 , H01L29/6659
摘要： One or more aspects of the present invention relate to forming a transistor while passivating electrically active defects associated with a top portion of a layer of high-k dielectric material. The layer of high-k dielectric material is utilized to establish a high-k gate dielectric in the transistor. A gate electrode layer is formed over the layer of high-k dielectric material, and is patterned to form a gate structure that includes a gate electrode and the high-k gate dielectric. The electrically active defects are passivated utilizing materials containing dopants that are attracted to and neutralize the defects. The passivated defects thus do not interfere with other transistor doping processes (e.g., forming source and drain regions) and do not adversely affect resulting semiconductor device performance, reliability and yield.
摘要翻译： 本发明的一个或多个方面涉及形成晶体管，同时钝化与高k电介质材料层的顶部相关联的电活性缺陷。 高k介电材料层用于在晶体管中建立高k栅极电介质。 栅电极层形成在高k电介质材料层上，并被图案化以形成包括栅电极和高k栅电介质的栅结构。 使用含有被吸引并中和缺陷的掺杂剂的材料来钝化电活性缺陷。 钝化的缺陷因此不干扰其它晶体管掺杂过程（例如，形成源极和漏极区），并且不会对所得到的半导体器件性能，可靠性和产量产生不利影响。
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8.发明授权Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing 有权双层沉积以避免在高K栅介质处理期间的不希望的界面反应公开(公告)号：US06696332B2
公开(公告)日：2004-02-24
申请号：US10176596
申请日：2002-06-21
IPC分类号： H01L218238
CPC分类号： H01L21/28185 , H01L21/2652 , H01L21/28194 , H01L21/28202 , H01L21/28238 , H01L21/28291 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Methods are disclosed for forming gate dielectrics for MOSFET transistors, wherein a bilayer deposition of a nitride layer and an oxide layer are used to form a gate dielectric stack. The nitride layer is formed on the substrate to prevent oxidation of the substrate material during deposition of the oxide layer, thereby avoiding or mitigating formation of low-k interfacial layer.
摘要翻译： 公开了用于形成用于MOSFET晶体管的栅极电介质的方法，其中使用氮化物层和氧化物层的双层沉积来形成栅极电介质叠层。 在衬底上形成氮化物层以防止氧化物层沉积期间衬底材料的氧化，从而避免或减轻低k界面层的形成。
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公开(公告)号：US06656852B2
公开(公告)日：2003-12-02
申请号：US10006081
申请日：2001-12-06
IPC分类号： H01L21302
CPC分类号： H01L21/28194 , H01L21/31111 , H01L29/51 , H01L29/517 , H01L29/518
摘要： One aspect of the invention relates to a method of etching a high-k dielectric. The method involves removing an exposed portion of a high-k dielectric layer from a substrate by wet etching with a solution comprising water, a strong acid, an oxidizing agent, and a fluorine compound. The etching solution provides selectivity towards the high-k film against insulating materials and polysilicon and is therefore useful in manufacturing FETs.
摘要翻译： 本发明的一个方面涉及一种蚀刻高k电介质的方法。 该方法包括通过用包含水，强酸，氧化剂和氟化合物的溶液的湿蚀刻从基底去除高k电介质层的暴露部分。 蚀刻溶液提供了对绝缘材料和多晶硅的高k膜的选择性，因此可用于制造FET。
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10.发明申请Method to prevent defects on SRAM cells that incorporate selective epitaxial regions 有权防止并入选择性外延区域的SRAM单元上的缺陷的方法公开(公告)号：US20070290192A1
公开(公告)日：2007-12-20
申请号：US11453190
申请日：2006-06-14
IPC分类号： H01L31/00
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L27/088 , H01L27/11 , H01L27/1104 , H01L29/66636 , H01L29/7848
摘要： An SRAM device and method of forming MOS transistors of the device having reduced defects associated with selective epitaxial growth in moat tip regions is discussed. The SRAM device comprises a core region and a logic region, logic transistors within the logic region of the SRAM, and selective epitaxial regions grown on both source and drain regions; and memory cell transistors within the core region of the SRAM, and having the selective epitaxial regions grown on only one of the source and drain regions. One method of forming the MOS transistors of the SRAM cell comprises forming a gate structure over a first conductivity type substrate to define a channel therein, masking one of the source and drain regions in the core region, forming a recess in the substrate of the unmasked side of the channel, epitaxially growing SiGe in the recess, removing the mask, and forming the source and drain extension regions in source/drain regions.
摘要翻译： 讨论了一种SRAM器件和形成具有减少的与护套护耳区域中的选择性外延生长有关的缺陷的器件的MOS晶体管的方法。 SRAM器件包括核心区域和逻辑区域，在SRAM的逻辑区域内的逻辑晶体管以及在源极和漏极区域上生长的选择性外延区域; 以及在SRAM的核心区域内的存储单元晶体管，并且仅在源极和漏极区域之一上生长选择性外延区域。 形成SRAM单元的MOS晶体管的一种方法包括在第一导电类型衬底上形成栅极结构以在其中限定沟道，掩蔽芯区域中的源区和漏区之一，在未屏蔽的衬底中形成凹陷 在沟槽中外延生长SiGe，去除掩模，以及在源极/漏极区域中形成源极和漏极延伸区域。
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