公开(公告)号：US07612749B2

公开(公告)日：2009-11-03

申请号：US10379481

申请日：2003-03-04

申请人： Frank Robert Libsch ,  James Lawrence Sanford

发明人： Frank Robert Libsch ,  James Lawrence Sanford

IPC分类号： G09G3/32

CPC分类号： H01L29/78648 ,  G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0847 ,  G09G2300/0866 ,  G09G2320/043 ,  H01L27/12 ,  H01L27/3244

摘要： A pixel circuit includes a light emitting device, a storage device configured to represent a level of illumination, and a driving device used to drive the light emitting device. Configuring the storage device includes changing a voltage difference across the storage device to a level larger than a threshold voltage of the driving device. The driving device reduces driving of the light emitting device while the storage device is being configured. After the storage device has been configured, the driving device is permitted to drive the light emitting device to emit light having a luminance level corresponding to the level of illumination represented by the storage device.

摘要翻译： 像素电路包括发光装置，被配置为表示照明水平的存储装置和用于驱动发光装置的驱动装置。 配置存储设备包括将存储设备上的电压差改变到大于驱动设备的阈值电压的电平。 驱动装置在配置存储装置的同时减少发光装置的驱动。 在已经配置存储装置之后，允许驱动装置驱动发光装置发射具有与由存储装置表示的照明水平相对应的亮度级的光。

公开(公告)号：US06734636B2

公开(公告)日：2004-05-11

申请号：US10176931

申请日：2002-06-21

申请人： James Lawrence Sanford ,  Frank Robert Libsch

发明人： James Lawrence Sanford ,  Frank Robert Libsch

IPC分类号： G09G310

CPC分类号： G09G3/325 ,  G09G2300/0842 ,  G09G2300/0866 ,  G09G2310/0256 ,  G09G2320/02 ,  G09G2320/043

摘要： There is provided a method for driving an organic light emitting diode (OLED) pixel circuit. The method includes applying a first signal to a terminal of the OLED when setting a state of the pixel circuit, and applying a second signal to the terminal when viewing the state. There is also provided a driver for an OLED pixel circuit, where the driver employs this method.

摘要翻译： 提供了一种用于驱动有机发光二极管（OLED）像素电路的方法。 该方法包括当设置像素电路的状态时向OLED的端子施加第一信号，以及在观看状态时向终端施加第二信号。 还提供了用于OLED像素电路的驱动器，其中驱动器采用该方法。

公开(公告)号：US07038392B2

公开(公告)日：2006-05-02

申请号：US10672373

申请日：2003-09-26

申请人： Frank Robert Libsch ,  James Lawrence Sanford

发明人： Frank Robert Libsch ,  James Lawrence Sanford

IPC分类号： G09G3/10

CPC分类号： G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0866 ,  G09G2310/0251 ,  G09G2310/0254 ,  G09G2320/043 ,  G09G2330/06

摘要： An active matrix display includes a plurality of pixels arranged in an array, a first transistor and a second transistor associated with each pixel, the first and second transistors positioned within the array for controlling current flow through each pixel, a light emitting diode associated with each pixel; and a storage capacitor associated with each pixel, wherein, during a time period for establishment of a threshold voltage on the storage capacitor for the first transistor, a voltage equal to the sum of the threshold voltage and a voltage for compensating for turnoff of the second transistor is established on the storage capacitor.

摘要翻译： 有源矩阵显示器包括排列成阵列的多个像素，与每个像素相关联的第一晶体管和第二晶体管，位于阵列内的第一和第二晶体管用于控制每个像素的电流，与每个像素相关联的发光二极管 像素 以及与每个像素相关联的存储电容器，其中，在用于在所述第一晶体管的存储电容器上建立阈值电压的时间段期间，将等于所述阈值电压和用于补偿所述第二晶体管的截止电压的电压之和的电压 晶体管建立在存储电容上。

公开(公告)号：US06667791B2

公开(公告)日：2003-12-23

申请号：US10177243

申请日：2002-06-21

申请人： James Lawrence Sanford ,  Frank Robert Libsch

发明人： James Lawrence Sanford ,  Frank Robert Libsch

IPC分类号： H05B3332

CPC分类号： H01L27/3281 ,  G02F1/13336 ,  G02F1/1345 ,  G02F1/13452 ,  G02F2201/42 ,  H01L27/3288 ,  H01L27/3293 ,  H01L51/5203

摘要： There is provided a display apparatus. The apparatus includes (1) a substrate, (2) a display element disposed on the substrate, the display element having (a) a first electrical conductor, (b) a second electrical conductor, and (c) a light switching material disposed between the first electrical conductor and the second electrical conductor, and (3) a via through the substrate for electrically coupling a signal to the first electrical conductor.

公开(公告)号：US5790090A

公开(公告)日：1998-08-04

申请号：US730986

申请日：1996-10-16

申请人： Frank Robert Libsch ,  Eugene Stewart Schlig

发明人： Frank Robert Libsch ,  Eugene Stewart Schlig

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G2300/0876 ,  G09G3/3614

摘要： An active matrix liquid crystal display (AMLCD) and driving method is disclosed. The AMLCD has matrix-arranged pixel assemblies each having display electrodes. A gate line for carrying gate line pulses is connected to a control port of a row of semiconductor devices, which may be thin film transistors (TFTs). Each TFT has an output port connected to the display electrodes. In addition, a data line is connected to an input port of a column of the TFTs. A bootstrap line is capacitively connected to the display electrodes of adjacent rows. This reduce the number of bootstrap lines to half the number of gate and data lines. A bootstrap pulse timing and generating circuit is connected to the bootstrap line to provide a bootstrap pulse that shifts voltages on the display electrodes in only one direction. The bootstrap pulse has a first edge of a first polarity occurring before or during gate pulses carried on a gate line, and a second edge of a second polarity occurring after the gate line pulses.

摘要翻译： 公开了一种有源矩阵液晶显示器（AMLCD）和驱动方法。 AMLCD具有每个具有显示电极的矩阵排列的像素组件。 用于承载栅极线脉冲的栅极线连接到一行半导体器件的控制端口，其可以是薄膜晶体管（TFT）。 每个TFT具有连接到显示电极的输出端口。 此外，数据线连接到TFT的列的输入端口。 引导线电容连接到相邻行的显示电极。 这将引导线的数量减少到门和数据线的数量的一半。 自举脉冲定时和产生电路连接到引导线，以提供自举脉冲，其仅在一个方向上移动显示电极上的电压。 自举脉冲具有第一极性的第一边缘，出现在栅极线上携带的栅极脉冲之前或之后，以及出现在栅极线脉冲之后的第二极性的第二边缘。

公开(公告)号：US06940300B1

公开(公告)日：2005-09-06

申请号：US09239323

申请日：1999-01-28

申请人： Leslie Charles Jenkins ,  Frank Robert Libsch ,  Michael Patrick Mastro ,  Robert Wayne Nywening ,  Robert John Polastre

发明人： Leslie Charles Jenkins ,  Frank Robert Libsch ,  Michael Patrick Mastro ,  Robert Wayne Nywening ,  Robert John Polastre

IPC分类号： G01R31/00 ,  G09G3/00 ,  G09G3/36

CPC分类号： G09G3/006 ,  G09G3/3648

摘要： A device for use in a display system including an array of pixel cells formed on a substrate. Each pixel cell being coupled to at least one gate line of a plurality of gate lines formed on the substrate and at least one data line of a plurality of data lines being formed on the substrate. The device includes first and second transistors formed on the substrate. Each transistor has a gate electrode and first and second electrodes defining a serpentine channel region there between voltage applied to the gate electrode controls conductivity of the channel region. Preferably, a common electrode includes one of the first and second electrodes of the first transistor and one of the first and second electrodes of the second transistor. The first and second transistors are preferably coupled between a gate line (or data line) and respective probe pads formed on the substrate and selectively couple the respective probe pad to the gate line (or data line) during a test routine whereby charge is written to, stored, and read from the array of pixel cells.

摘要翻译： 一种用于显示系统的装置，包括形成在基板上的像素单元阵列。 每个像素单元耦合到在衬底上形成的多个栅极线的至少一个栅极线，并且多个数据线的至少一条数据线被形成在衬底上。 该器件包括形成在衬底上的第一和第二晶体管。 每个晶体管具有栅极电极，并且在施加到栅电极的电压之间限定沟道区域的导电性的第一和第二电极限定蛇形沟道区域。 优选地，公共电极包括第一晶体管的第一和第二电极之一以及第二晶体管的第一和第二电极之一。 第一和第二晶体管优选地耦合在栅极线（或数据线）和形成在衬底上的各个探针焊盘之间，并且在测试程序期间选择性地将各个探针焊盘耦合到栅线（或数据线），从而将电荷写入 ，从像素单元阵列存储和读取。

公开(公告)号：US06211851B1

公开(公告)日：2001-04-03

申请号：US09311004

申请日：1999-05-13

申请人： Shui-Chih Alan Lien ,  Frank Robert Libsch

发明人： Shui-Chih Alan Lien ,  Frank Robert Libsch

IPC分类号： G09G336

CPC分类号： G09G3/3648 ,  G09G3/2011 ,  G09G3/3614 ,  G09G2310/0251 ,  G09G2320/0209

摘要： The elimination of crosstalk between data lines and pixel cells in a thin film transistor/liquid crystal display is accomplished by applying a precharge voltage level for a given data signal level which also provides an equivalent to a compensation voltage for a prior scan line to a given data line for a time period less than the standard scan line period of the display, and applying the data signal to the given data line for the remainder of the scan line period.

摘要翻译： 在薄膜晶体管/液晶显示器中消除数据线和像素单元之间的串扰是通过对给定数据信号电平施加预充电电压电平来实现的，该给定数据信号电平也提供等于给定的先前扫描线的补偿电压 数据线小于显示器的标准扫描线周期的时间段，并且将数据信号施加到扫描线周期的其余部分的给定数据线。

公开(公告)号：US5940057A

公开(公告)日：1999-08-17

申请号：US528168

申请日：1995-09-14

申请人： Shui-Chih Alan Lien ,  Frank Robert Libsch

发明人： Shui-Chih Alan Lien ,  Frank Robert Libsch

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3648 ,  G09G2310/0251 ,  G09G2320/0209 ,  G09G3/2011 ,  G09G3/3614

摘要： The elimination of crosstalk between data lines and pixel cells in a thin film transistor/liquid crystal display is accomplished by applying a precharge voltage level for a given data signal level which also provides an equivalent to a compensation voltage for a prior scan line to a given data line for a time period less than the standard scan line period of the display, and applying the data signal to the given data line for the remainder of the scan line period.

摘要翻译： 在薄膜晶体管/液晶显示器中消除数据线和像素单元之间的串扰是通过对给定数据信号电平施加预充电电压电平来实现的，该给定数据信号电平也提供等于给定的先前扫描线的补偿电压 数据线小于显示器的标准扫描线周期的时间段，并且将数据信号施加到扫描线周期的其余部分的给定数据线。

公开(公告)号：US20080310808A1

公开(公告)日：2008-12-18

申请号：US11764447

申请日：2007-06-18

申请人： David Michael Fried ,  Philip Charles Danby Hobbs ,  Nancy Carolyn LaBianca ,  Frank Robert Libsch

发明人： David Michael Fried ,  Philip Charles Danby Hobbs ,  Nancy Carolyn LaBianca ,  Frank Robert Libsch

IPC分类号： G02B6/10 ,  C23F1/02

CPC分类号： G02B6/136

摘要： A photonic waveguide structure includes a first photonic waveguide layer located over a substrate. A sidewall cladding layer is located cladding a sidewall, but not covering a top, of the first photonic waveguide layer. A second photonic waveguide layer may be located upon the top of the sidewall cladding layer while contacting, but not straddling, the first photonic waveguide layer. The sidewall cladding layer protects the first photonic waveguide layer from environmental exposure, thus providing enhanced performance of a photonic waveguide structure. A planarizing sidewall cladding layer allows the fabrication of optical chips with multiple layers of lithographically defined devices.

摘要翻译： 光子波导结构包括位于衬底上的第一光子波导层。 侧壁包层定位为包覆第一光子波导层的侧壁但不覆盖顶部。 第二光子波导层可以位于侧壁包层的顶部，同时接触但不跨越第一光子波导层。 侧壁包覆层保护第一光子波导层免受环境暴露，从而提供光子波导结构的增强的性能。 平面化的侧壁包层允许制造具有多层光刻定义的器件的光学芯片。

公开(公告)号：US06437596B1

公开(公告)日：2002-08-20

申请号：US09239325

申请日：1999-01-28

申请人： Leslie Charles Jenkins ,  Frank Robert Libsch ,  Michael Patrick Mastro ,  Robert Wayne Nywening ,  Robert John Polastre

发明人： Leslie Charles Jenkins ,  Frank Robert Libsch ,  Michael Patrick Mastro ,  Robert Wayne Nywening ,  Robert John Polastre

IPC分类号： G01R3100

CPC分类号： G09G3/006

摘要： An improved apparatus for testing an array of pixel cells formed on a substrate is provided. Each pixel cell is coupled to at least one gate line of a plurality of gate lines formed on the substrate and at least one data line of a plurality of data lines formed on the substrate. The gate lines and/or data lines are partitioned into a plurality of groups. For each particular group, a first probe pad and select logic is formed on said substrate. The select logic, which is coupled between the first probe pad and the lines of the particular group, selectively couples the first probe pad to the lines of said particular group based upon first control signals supplied to the select logic during a test routine whereby charge is written to, stored, and read from the array of pixel cells. In addition, a second probe pad and hold logic for each particular group may be formed on the substrate. The hold logic, which is coupled between the second probe pad and the lines of the particular group, selectively couples the second probe pad to the lines of the particular group based upon second control signals supplied to the hold logic during the test routine. The apparatus provides a flexible interface between the array under test and the test system, which minimizes the redesign costs when the size and/or resolution of the array under test is varied.

摘要翻译： 提供了一种用于测试形成在衬底上的像素单元阵列的改进的装置。 每个像素单元被耦合到形成在衬底上的多个栅极线的至少一个栅极线和形成在衬底上的多条数据线的至少一条数据线。 栅极线和/或数据线被划分成多个组。 对于每个特定组，在所述衬底上形成第一探针焊盘和选择逻辑。 耦合在第一探针焊盘和特定组的线之间的选择逻辑基于在测试程序期间提供给选择逻辑的第一控制信号，将第一探针焊盘选择性地耦合到所述特定组的线， 写入，存储和从像素单元阵列读取。 此外，可以在衬底上形成用于每个特定组的第二探针焊盘和保持逻辑。 耦合在第二探针焊盘和特定组的线之间的保持逻辑基于在测试例程期间提供给保持逻辑的第二控制信号，将第二探针焊盘选择性地耦合到特定组的线。 该装置在待测阵列和测试系统之间提供灵活的接口，当测试中的阵列的尺寸和/或分辨率变化时，可最大限度地减少重新设计成本。