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公开(公告)号：US06049476A
公开(公告)日：2000-04-11
申请号：US126944
申请日：1998-07-31
IPC分类号： G11C7/00 , G11C5/00 , G11C5/02 , G11C11/00 , G11C11/401
摘要： A high memory capacity dual in-line memory module (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system including a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities.
摘要翻译： 一种用于基于目录的分布式共享存储器多处理器计算机系统的高存储容量双列直插式存储器模块（DIMM），包括用于存储数据的数据存储器和用于存储对应于至少一部分的状态或目录信息的状态存储器 的数据。 DIMM允许独立访问数据和状态信息。 DIMM可以配置成多个存储容量。
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公开(公告)号：US5686730A
公开(公告)日：1997-11-11
申请号：US747976
申请日：1996-11-12
申请人： James P. Laudon , Daniel E. Lenoski , John Manton
发明人： James P. Laudon , Daniel E. Lenoski , John Manton
摘要： A high memory capacity DIMM for use in a directory-based, distributed shared memory multiprocessor computer system includes a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM is configured for use in a DIMM pair. In the DIMM pair, a first DIMM includes a first data memory having first and second memory bank portions for storing data, and a first state memory configured to store state information corresponding to data stored in a first memory bank. A second DIMM includes a second data memory having third and fourth memory bank portions for storing data, and a second state memory configured to store state information corresponding to data stored in a second memory bank. The first memory bank is formed from the first memory bank portion and the third memory bank portion. The second memory bank is formed from the second memory bank portion and the fourth memory bank portion.
摘要翻译： 用于基于目录的分布式共享存储器多处理器计算机系统中的高存储容量DIMM包括用于存储数据的数据存储器和用于存储对应于数据的至少一部分的状态或目录信息的状态存储器。 DIMM允许独立访问数据和状态信息。 DIMM配置为用于DIMM对。 在DIMM对中，第一DIMM包括具有用于存储数据的第一和第二存储体部分的第一数据存储器，以及配置为存储对应于存储在第一存储体中的数据的状态信息的第一状态存储器。 第二DIMM包括具有用于存储数据的第三和第四存储体部分的第二数据存储器，以及配置为存储对应于存储在第二存储体中的数据的状态信息的第二状态存储器。 第一存储体由第一存储体部分和第三存储体部分形成。 第二存储体由第二存储体部分和第四存储体部分形成。
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公开(公告)号：US5790447A
公开(公告)日：1998-08-04
申请号：US747975
申请日：1996-11-12
申请人： James P. Laudon , Daniel E. Lenoski , John Manton
发明人： James P. Laudon , Daniel E. Lenoski , John Manton
摘要： A high memory capacity dual in-line memory modules (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system includes a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities.
摘要翻译： 用于基于目录的分布式共享存储器多处理器计算机系统中的高存储容量双列直插存储器模块（DIMM）包括用于存储数据的数据存储器和用于存储对应于至少一部分的状态或目录信息的状态存储器 的数据。 DIMM允许独立访问数据和状态信息。 DIMM可以配置成多个存储容量。
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4.发明授权Method and apparatus for exception handling in pipeline processors having mismatched instruction pipeline depths 失效在管道处理器中异常处理的方法和装置具有指令流水线深度不匹配
公开(公告)号：US5193158A
公开(公告)日：1993-03-09
申请号：US780527
申请日：1991-10-18
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/3863
摘要： Method and apparatus for sequentially executing a plurality of pipelined instruction words of a program in which each instruction has independently selectable execution cycle count latencies. After the occurrence of an exception, instructions are identified which began after the instruction that caused the exception, and which have completed execution before execution of the exception provoking instruction was inhibited. Detection of an exception causes the processor to inhibit further execution of the exception provoking instruction. Pending instructions, which have yet to complete their execution prior to the inhibition of the exception provoking instruction, are similarly inhibited from further execution. Subsequently, the exception is serviced and the exception inducing instruction is restarted for re-execution in the processor. Pending instructions are subsequently re-executed in the sequence of their occurrence at the time the exception provoking instruction caused the processor to inhibit further instruction execution. Completed instructions are not re-executed. Applicable to computing systems having a plurality of processors, of either the same or different type such as floating point and integer processors, the method and apparatus inhibits all such further execution of plural processors upon the detection of an exception in one of the processors. In processors other than the processors serving the exception, no-op instructions are executed until the processor servicing the exception causes pending instructions to be re-executed, at which time the other processors also re-execute instructions which were pending at the time further execution of the instructions was inhibited.
摘要翻译： 用于顺序地执行程序的多个流水线指令字的方法和装置，其中每个指令具有独立可选的执行周期计数延迟。 在发生异常之后，在引发异常的指令之后，在执行异常发起指令之前已经完成执行的指令被禁止的指令被识别。 检测异常会导致处理器禁止进一步执行异常发起指令。 在禁止异常激发指令之前还没有完成其执行的待处理指令同样被禁止进一步执行。 随后，异常被处理并且重新启动异常诱导指令以在处理器中重新执行。 随后的指令随后在异常发出指令引起处理器禁止进一步指令执行时按其发生顺序重新执行。 完成的指令不会重新执行。 适用于具有多个相同或不同类型的处理器（如浮点和整数处理器）的计算系统，所述方法和装置在检测到处理器之一中的异常时，禁止所有进一步执行多个处理器。 在服务于异常的处理器之外的处理器中，执行无操作指令，直到处理异常的处理器导致待执行的指令被重新执行，此时其他处理器还重新执行在进一步执行时待处理的指令 的说明被禁止。
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5.发明授权Data processing system for concurrent dispatch of instructions to multiple functional units 失效数据处理系统，用于将指令并发发送到多个功能单元
公开(公告)号：US5051885A
公开(公告)日：1991-09-24
申请号：US255105
申请日：1988-10-07
申请人： John S. Yates, Jr. , Stephen J. Ciavaglia , John Manton , Michael Kahaiyan , Richard G. Bahr , Barry J. Flahive
发明人： John S. Yates, Jr. , Stephen J. Ciavaglia , John Manton , Michael Kahaiyan , Richard G. Bahr , Barry J. Flahive
CPC分类号： G06F9/3889 , G06F9/30149 , G06F9/321 , G06F9/3814 , G06F9/3816 , G06F9/3853 , G06F9/3885
摘要： Apparatus and method for concurrent dispatch of instruction words which selectively comprise instruction components which are separately and substantially simultaneously received by distinct floating point and integer functional units. The instruction words are powers of 2 in length, (measured in terms of the smallest machine addressable unit) typically a 4 byte longword and an 8 byte quadword aligned to the natural boundaries also corresponding to powers of 2. To provide maximum operating efficiency, each functional (or processing) unit executes a component of an instruction word during an execution cycle. The type and length of the instruction word are indicated by one of the bit fields of the instruction word, which permits the apparatus to properly detect, store and transfer the instruction word to the appropriate functional unit. The invention combines the encoding efficiency of variable length instruction combined combined with the enhanced processing speed of simultaneous operation of all available functional units, to provide the execution efficiency of systems with a single instruction length.
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