公开(公告)号：US20160043232A1

公开(公告)日：2016-02-11

申请号：US14920647

申请日：2015-10-22

Applicant: Japan Display Inc.

Inventor： Norihiro UEMURA ,  Takeshi NODA ,  Hidekazu MIYAKE ,  Isao SUZUMURA

IPC: H01L29/786 ,  G02F1/1335 ,  G02F1/1368 ,  H01L27/12

CPC classification number: H01L29/78606 ,  G02F1/133602 ,  G02F1/1368 ,  H01L27/1225 ,  H01L29/7869

Abstract: A thin film transistor includes, an insulating substrate, a gate electrode provided on an upper surface of the insulating substrate, a gate insulating film formed so as to cover the gate electrode, an oxide semiconductor layer provided on the gate insulating film, a channel protective layer provided at least on an upper surface of the oxide semiconductor layer, and a source electrode and a drain electrode provided so as to come into contact with the oxide semiconductor layer, wherein the channel protective layer is formed such that the film density of a portion provided so as to come into contact with the oxide semiconductor layer is higher than the film density of a portion distant from the oxide semiconductor layer.

公开(公告)号：US20140362059A1

公开(公告)日：2014-12-11

申请号：US14300257

申请日：2014-06-10

Applicant: Japan Display Inc.

Inventor： Norihiro UEMURA ,  Hidekazu MIYAKE ,  Takeshi NODA ,  Isao SUZUMURA ,  Yohei YAMAGUCHI

IPC: H01L27/12 ,  G09G5/00 ,  H01L29/786

CPC classification number: G09G5/00 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/7869

Abstract: A thin film transistor includes a drain electrode layer and a source electrode layer that are formed above an oxide semiconductor layer via an insulating film. The drain electrode layer and the source electrode layer are electrically connected with the oxide semiconductor layer via through-holes formed in the insulating film. A first through-hole that electrically connects the drain electrode layer with the oxide semiconductor layer and a second through-hole that electrically connects the source electrode layer with the oxide semiconductor layer each include two or more through-holes that are arranged in parallel in a channel width direction of the thin film transistor. A total width of opening widths of the first or second through-holes in the channel width direction is a channel width of the thin film transistor.

Abstract translation: 薄膜晶体管包括通过绝缘膜形成在氧化物半导体层上方的漏电极层和源极电极层。 漏电极层和源电极层通过形成在绝缘膜中的通孔与氧化物半导体层电连接。 将漏电极层与氧化物半导体层电连接的第一通孔和将源电极层与氧化物半导体层电连接的第二通孔各自包括两个或更多个平行布置的通孔， 薄膜晶体管的沟道宽度方向。 沟道宽度方向上的第一或第二通孔的开口宽度的总宽度是薄膜晶体管的沟道宽度。

公开(公告)号：US20130334524A1

公开(公告)日：2013-12-19

申请号：US13915671

申请日：2013-06-12

Applicant: Japan Display Inc.

Inventor： Hidekazu MIYAKE ,  Norihiro UEMURA ,  Takeshi NODA ,  Isao SUZUMURA ,  Toshiki KANEKO

IPC: H01L27/12

CPC classification number: H01L27/1244 ,  H01L27/1225 ,  H01L27/1288 ,  H01L27/3244

Abstract: The present invention provides a display device having: gate electrodes formed on a transparent substrate; a gate insulating film for covering the gate electrodes; an oxide semiconductor formed on the gate insulating film; drain electrodes and source electrodes formed at a distance from each other with channel regions of the oxide semiconductor in between; an interlayer capacitor film for covering the drain electrodes and source electrodes; common electrodes formed on top of the interlayer capacitor film; and pixel electrodes formed so as to face the common electrodes, and wherein an etching stopper layer for covering the channel regions is formed between the oxide semiconductor and the drain electrodes and source electrodes, the drain electrodes are a multilayer film where a transparent conductive film and a metal film are layered on top of each other, and the drain electrodes and source electrodes make direct contact with the oxide semiconductor.

Abstract translation: 本发明提供一种显示装置，具有：形成在透明基板上的栅电极; 用于覆盖栅电极的栅极绝缘膜; 形成在栅极绝缘膜上的氧化物半导体; 漏电极和源极之间形成有一定距离的氧化物半导体的沟道区; 用于覆盖漏电极和源电极的层间电容膜; 公共电极形成在层间电容器膜的顶部; 以及形成为与公共电极相对的像素电极，并且其中在氧化物半导体与漏电极和源电极之间形成用于覆盖沟道区的蚀刻停止层，漏电极是多层膜，其中透明导电膜和 金属膜层叠在一起，漏电极和源电极与氧化物半导体直接接触。

公开(公告)号：US20140307194A1

公开(公告)日：2014-10-16

申请号：US14245102

申请日：2014-04-04

Applicant: Japan Display Inc.

Inventor： Isao SUZUMURA ,  Norihiro UEMURA ,  Takeshi NODA ,  Hidekazu MIYAKE ,  Yohei YAMAGUCHI

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78696 ,  G02F1/133345 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/1337 ,  G02F1/134309 ,  G02F1/1368 ,  G02F2001/133357 ,  H01L27/1225 ,  H01L27/1285 ,  H01L29/24 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78693

Abstract: In a bottom gate thin film transistor using a first oxide semiconductor layer as a channel layer, the first oxide semiconductor layer and second semiconductor layers include In and O. An (O/In) ratio of the second oxide semiconductor layers is equal to or larger than that of the first oxide semiconductor layer, and a film thickness thereof is thicker than that of the first oxide semiconductor layer.

Abstract translation: 在使用第一氧化物半导体层作为沟道层的底栅极薄膜晶体管中，第一氧化物半导体层和第二半导体层包括In和O.第二氧化物半导体层的（O / In）比等于或大于 比第一氧化物半导体层的厚度厚，其厚度比第一氧化物半导体层厚。

公开(公告)号：US20160284867A1

公开(公告)日：2016-09-29

申请号：US15172576

申请日：2016-06-03

Applicant: Japan Display Inc.

Inventor： Isao SUZUMURA ,  Norihiro UEMURA ,  Takeshi NODA ,  Hidekazu MIYAKE ,  Yohei YAMAGUCHI

IPC: H01L29/786 ,  H01L27/12 ,  G02F1/1368 ,  G02F1/1335 ,  G02F1/1337 ,  G02F1/1343 ,  H01L29/24 ,  G02F1/1333

CPC classification number: H01L29/78696 ,  G02F1/133345 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/1337 ,  G02F1/134309 ,  G02F1/1368 ,  G02F2001/133357 ,  H01L27/1225 ,  H01L27/1285 ,  H01L29/24 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78693

Abstract: In a bottom gate thin film transistor using a first oxide semiconductor layer as a channel layer, the first oxide semiconductor layer and second semiconductor layers include In and O. An (O/In) ratio of the second oxide semiconductor layers is equal to or larger than that of the first oxide semiconductor layer, and a film thickness thereof is thicker than that of the first oxide semiconductor layer.

Abstract translation: 在使用第一氧化物半导体层作为沟道层的底栅极薄膜晶体管中，第一氧化物半导体层和第二半导体层包括In和O.第二氧化物半导体层的（O / In）比等于或大于 比第一氧化物半导体层的厚度厚，其厚度比第一氧化物半导体层厚。

公开(公告)号：US20140054583A1

公开(公告)日：2014-02-27

申请号：US13965418

申请日：2013-08-13

Applicant: Japan Display Inc.

Inventor： Norihiro UEMURA ,  Takeshi NODA ,  Hidekazu MIYAKE ,  Isao SUZUMURA

IPC: H01L33/00

CPC classification number: H01L33/0041 ,  H01L21/77 ,  H01L27/1225 ,  H01L29/7869

Abstract: A gate insulating film has a convex portion conforming to a surface shape of a gate electrode and a step portion that changes in height from a periphery of the gate electrode along the surface of the gate electrode. An oxide semiconductor layer is disposed on the gate insulating film so as to have a transistor constituting region having a channel region, a source region, and a drain region in a continuous and integral manner and a covering region being separated from the transistor constituting region and covering the step portion of the gate insulating film. A channel protective layer is disposed on the channel region of the oxide semiconductor layer. A source electrode and a drain electrode are disposed in contact respectively with the source region and the drain region of the oxide semiconductor layer. A passivation layer is disposed on the source electrode and the drain electrode.

Abstract translation: 栅极绝缘膜具有符合栅电极的表面形状的凸部和沿着栅电极的表面从栅电极的周边高度变化的台阶部。 在栅极绝缘膜上设置氧化物半导体层，以具有沟道区域，源极区域和漏极区域的晶体管构成区域，并且与晶体管构成区域分离的覆盖区域和 覆盖栅极绝缘膜的台阶部分。 沟道保护层设置在氧化物半导体层的沟道区上。 源极电极和漏电极分别与氧化物半导体层的源极区域和漏极区域接触。 钝化层设置在源电极和漏电极上。