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    TTL buffer circuit incorporating active pull-down transistor
    3.
    发明授权
    TTL buffer circuit incorporating active pull-down transistor 失效
    包含有源下拉晶体管的TTL缓冲电路

    公开(公告)号：US4634898A

    公开(公告)日：1987-01-06

    申请号：US554474

    申请日：1983-11-22

    申请人： Gary Gouldsberry ,  Albert Chan ,  Cyrus Tsui ,  Mark Fitzpatrick

    发明人： Gary Gouldsberry ,  Albert Chan ,  Cyrus Tsui ,  Mark Fitzpatrick

    IPC分类号： H03K19/013 ,  H03K19/088 ,  H03K17/04 ,  H03K17/60

    CPC分类号： H03K19/013 ,  H03K19/0136 ,  H03K19/088

    摘要： A unique double inversion buffer has a first means to invert and isolate the digital input signal, a second means to reinvert and further isolate the input signal, and an output means including an output transistor 94. The double inversion buffer is configured with active pull-down means on the output transistor 92. The high-to-low propagation delay time and the low-to-high propagation delay times through the double inversion buffer and reduced by use of the active pull-down means. Rapid turnoff of the output transistor is accomplished by coupling a transistor to its base to instantaneously turn it off. In a preferred embodiment, a clamping circuit 201 is used to hold the output voltage at a maximum predetermined level to further reduce the time it takes to reduce the output voltage to the logical "0" state.

    摘要翻译： 独特的双反相缓冲器具有第一装置，用于反转和隔离数字输入信号，第二装置重新转换并进一步隔离输入信号，以及包括输出晶体管94的输出装置。双反相缓冲器配置有主动上拉电阻， 输出晶体管92的下降装置。通过双重反转缓冲器的高到低的传播延迟时间和低到高的传播延迟时间通过使用有源下拉装置而减少。 输出晶体管的快速关断是通过将晶体管耦合到其基极来实时地将其截止的。 在优选实施例中，钳位电路201用于将输出电压保持在最大预定电平，以进一步减少将输出电压降低到逻辑“0”状态所花费的时间。

    Output circuit for a programmable logic array
    6.
    发明授权
    Output circuit for a programmable logic array 失效
    可编程逻辑阵列的输出电路

    公开(公告)号：US4684830A

    公开(公告)日：1987-08-04

    申请号：US715214

    申请日：1985-03-22

    申请人： Cyrus Tsui ,  Andrew K. L. Chan ,  Albert Chan ,  Mark E. Fitzpatrick ,  Zahid Ansari

    发明人： Cyrus Tsui ,  Andrew K. L. Chan ,  Albert Chan ,  Mark E. Fitzpatrick ,  Zahid Ansari

    IPC分类号： H03K19/177 ,  H03K19/20

    CPC分类号： H03K19/17716

    摘要： An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, the clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.

    摘要翻译： 为可编程逻辑阵列（PLA）集成电路提供输出电路（50）。 输出电路（50）包括一个触发器（52），该触发器存储来自阵列的给定的输出项。 触发器（52）包含设定输入引线（S）和复位输入引线（R）。 存在于设定输入，复位输入，时钟引脚的信号由PLA内的可编程逻辑产生。 提供了多路复用器（54），其接收触发器（52）的输出数据和构成触发器的输入数据的信号。 当设置和复位输入信号都为真时，多路复用器在多路复用器输出引线（60）上提供数据输入信号。 然而，如果设置和复位输入信号中的任何一个或两者都为假，则多路复用器（54）从多路复用器输出引线（60）上的触发器（52）提供Q输出信号。 复用器输出信号被呈现给三态缓冲器（62），其又驱动输出引脚。

    Method and structure for disabling and replacing defective memory in a PROM
    7.
    发明授权
    Method and structure for disabling and replacing defective memory in a PROM 失效
    用于禁用和替换PROM中的有缺陷的存储器的方法和结构

    公开(公告)号：US4654830A

    公开(公告)日：1987-03-31

    申请号：US675379

    申请日：1984-11-27

    申请人： H. T. Chua ,  Cyrus Tsui ,  Albert Chan ,  Gary Gouldsberry

    发明人： H. T. Chua ,  Cyrus Tsui ,  Albert Chan ,  Gary Gouldsberry

    IPC分类号： G11C7/00 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00

    CPC分类号： G11C29/78

    摘要： Means are provided for replacing a defective row (or column) of memory in a fuse-array PROM which comprises disabling the defective row and programming a redundant row to respond to the address of the defective row. Means are also provided for reducing the swing between high and low address voltages.The redundant row is connected via an AND gate through fuses to all ADDRESS and ADDRESS lines of the address buffer, so that the redundant row is always off until programmed. If a defective row is found, all memory cells in the defective row are disabled and the redundant row is programmed by selectively blowing fuses leading to the ADDRESS and ADDRESS lines thus causing the redundant row to respond to the address of the defective row.

    摘要翻译： 提供了用于替换熔丝阵列PROM中的存储器的有缺陷行（或列）的装置，其包括禁用缺陷行并编程冗余行以响应缺陷行的地址。 还提供了用于减小高和低地址电压之间的摆动的装置。 冗余行通过保险丝通过与门连接到地址缓冲区的所有ADDRESS和＆Upbar＆AS /线，以便冗余行始终关闭，直到编程为止。 如果找到有缺陷的行，则有缺陷的行中的所有存储单元被禁用，并且冗余行被编程，通过选择性地吹送导致ADDRESS和＆amp; upbar＆AS /线的熔丝，从而使得冗余行响应缺陷行的地址。

    Programmable logic device
    8.
    发明授权
    Programmable logic device 失效
    可编程逻辑器件

    公开(公告)号：US06255847B1

    公开(公告)日：2001-07-03

    申请号：US09083205

    申请日：1998-05-21

    申请人： Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

    发明人： Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

    IPC分类号： H03K19177

    CPC分类号： H03K19/17728 ,  H03K17/163

    摘要： An improved programmable logic device includes a set of I/O cells, a set of logic blocks, and a routing pool that provides connections among the logic blocks and the I/O cells. At least one of the logic blocks includes a programmable logic array that generates product term output signals on product term output lines. A first product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The first product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. Likewise, a second product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The second product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. The logic block further includes first and second output lines and a first programmable switching device that programmably couples the first output line to the output terminal of either the first or the second product term summing circuit. The logic block further includes a second programmable switching device that programmably couples the second output line to the output terminal of either the first or the second product term summing circuit. The programmable logic device has increased functional capacity. In addition, generating an interconnect solution to program the programmable logic device is made simpler by the present invention.

    摘要翻译： 改进的可编程逻辑器件包括一组I / O单元，一组逻辑块和提供逻辑块和I / O单元之间的连接的路由池。 至少一个逻辑块包括在产品项输出线上产生产品项输出信号的可编程逻辑阵列。 第一乘积项求和电路具有输入端子，其中至少一个耦合到产品项输出线。 第一乘积项求和电路响应于至少一个乘积项输出信号在输出端产生输出信号。 类似地，第二乘积项求和电路具有输入端子，其中至少一个耦合到产品项输出线。 第二乘积项求和电路响应于至少一个乘积项输出信号在输出端产生输出信号。 逻辑块还包括第一和第二输出线以及可编程地将第一输出线耦合到第一或第二乘积项求和电路的输出端的第一可编程开关装置。 逻辑块还包括可编程地将第二输出线耦合到第一或第二乘积项求和电路的输出端的第二可编程开关装置。 可编程逻辑器件具有增加的功能容量。 此外，通过本发明使得生成用于编程可编程逻辑器件的互连解决方案变得更简单。

    Programmable output voltage levels
    9.
    发明授权
    Programmable output voltage levels 失效
    可编程输出电压电平

    公开(公告)号：US6066977A

    公开(公告)日：2000-05-23

    申请号：US83336

    申请日：1998-05-21

    申请人： Bradley Felton ,  Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

    发明人： Bradley Felton ,  Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

    IPC分类号： H03K19/0185 ,  H03K17/16

    CPC分类号： H03K19/018585

    摘要： A circuit for providing programmable voltage output levels in a logic device includes a pull-up device for driving an output pad with either a first voltage output level or a second voltage output level. A charge pump generates a pumped voltage. A first clamp regulator, coupled to the charge pump and the pull-up device, receives a first reference signal. The first clamp regulator, in response to the first reference signal, generates a first voltage from which the first voltage output level is derived. A second clamp regulator, coupled to the pull-up device, receives a second reference signal. In response to the second reference signal, the second clamp regulator generates a second voltage from which the second voltage output level is derived. A passgate multiplexer is coupled to the first and second clamp regulators. The passgate multiplexer receives at least one output voltage select signal. In response to the at least one output voltage select signal the passgate multiplexer selects either the first voltage output level or the second voltage output level.

    摘要翻译： 用于在逻辑器件中提供可编程电压输出电平的电路包括用于以第一电压输出电平或第二电压输出电平驱动输出焊盘的上拉器件。 电荷泵产生泵浦电压。 耦合到电荷泵和上拉装置的第一钳位调节器接收第一参考信号。 第一钳位调节器响应于第一参考信号产生第一电压，从该第一电压导出第一电压输出电平。 耦合到上拉装置的第二钳位调节器接收第二参考信号。 响应于第二参考信号，第二钳位调节器产生从其导出第二电压输出电平的第二电压。 通道多路复用器耦合到第一和第二钳位调节器。 所述通道门多路复用器接收至少一个输出电压选择信号。 响应于至少一个输出电压选择信号，通道门复用器选择第一电压输出电平或第二电压输出电平。