公开(公告)号：US06809027B2

公开(公告)日：2004-10-26

申请号：US10165264

申请日：2002-06-06

申请人： Jay W. Strane ,  Hiroyuki Akatsu ,  David M. Dobuzinsky

发明人： Jay W. Strane ,  Hiroyuki Akatsu ,  David M. Dobuzinsky

IPC分类号： H01L214763

CPC分类号： H01L21/76897

摘要： A method for forming high-density self-aligned contacts and interconnect structures in a semiconductor device. A dielectric layer thick enough to contain both interconnect and contact structures is formed on a substrate. A patterned hardmask is formed on the dielectric layer to define both the interconnect and contact structures. The openings for interconnect features are first formed by partially etching the dielectric layer selective to the hardmask. A second mask (e.g., a resist) is used to define the contact openings, and the dielectric layer is etched through the second mask, also selective to the hardmask, to expose the diffusion regions to be contacted. The patterned hardmask is used to help define the contact openings. Conductive material is then deposited in the openings which results in contacts and interconnects that are self-aligned. By first forming the openings for both interconnect and contacts, savings in processing steps may be obtained.

公开(公告)号：US06806177B2

公开(公告)日：2004-10-19

申请号：US10719861

申请日：2003-11-21

申请人： Jay W. Strane ,  Hiroyuki Akatsu ,  David M. Dobuzinsky

发明人： Jay W. Strane ,  Hiroyuki Akatsu ,  David M. Dobuzinsky

IPC分类号： H01L2144

CPC分类号： H01L21/76897

摘要： A method for forming high-density self-aligned contacts and interconnect structures in a semiconductor device. A dielectric layer thick enough to contain both interconnect and contact structures is formed on a substrate. A patterned hardmask is formed on the dielectric layer to define both the interconnect and contact structures. The openings for interconnect features are first formed by partially etching the dielectric layer selective to the hardmask. A second mask (e.g., a resist) is used to define the contact openings, and the dielectric layer is etched through the second mask, also selective to the hardmask, to expose the diffusion regions to be contacted. The patterned hardmask is used to help define the contact openings. Conductive material is then deposited in the openings which results in contacts and interconnects that are self-aligned. By first forming the openings for both interconnect and contacts, savings in processing steps may be obtained.

摘要翻译： 一种在半导体器件中形成高密度自对准触点和互连结构的方法。 在衬底上形成足够厚以容纳互连和接触结构的电介质层。 在电介质层上形成图形化的硬掩模以限定互连和接触结构。 用于互连特征的开口首先通过部分蚀刻对硬掩模有选择性的介电层而形成。 使用第二掩模（例如抗蚀剂）来限定接触开口，并且通过第二掩模蚀刻电介质层，也可以对硬掩模进行选择，以暴露待接触的扩散区域。 图案化的硬掩模用于帮助定义接触开口。 然后将导电材料沉积在开口中，这导致自对准的触点和互连。 通过首先形成用于互连和接触的开口，可以获得处理步骤的节省。

公开(公告)号：US06887785B1

公开(公告)日：2005-05-03

申请号：US10709564

申请日：2004-05-13

申请人： David M. Dobuzinsky ,  Carl J. Radens ,  Roy C. Iggulden ,  Jay W. Strane ,  Keith K. H. Wong

发明人： David M. Dobuzinsky ,  Carl J. Radens ,  Roy C. Iggulden ,  Jay W. Strane ,  Keith K. H. Wong

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76897

摘要： A semiconductor device with openings of differing depths in a substrate or layer is described, as are related methods for its manufacture. Through selective deposition of a single mask layer, whereby low aspect ratio openings are substantially coated while high aspect ratio are at most partially coated, subsequent etching of the substrate or layer is restricted to uncoated portions of the high aspect ratio openings. The result is a substrate or layer with openings of more than one depth using a single mask layer. In a second embodiment, the selective deposition of a single mask layer is utilized to etch a layer while protecting underlying structures from etching. In a third embodiment, the selective deposition of a single mask layer is utilized to etch an opening into a layer wherein the opening has a sub-lithographic diameter, i.e., the diameter of the opening is smaller than can be achieved with the particular lithographic technique employed.

摘要翻译： 描述了在衬底或层中具有不同深度的开口的半导体器件，以及用于其制造的相关方法。 通过选择性沉积单个掩模层，由此在高纵横比最多部分涂覆的同时基本上涂覆低纵横比的开口，随后对衬底或层的蚀刻被限制在高纵横比开口的未涂覆部分。 结果是使用单个掩模层的具有多于一个深度的开口的基底或层。 在第二实施例中，使用单个掩模层的选择性沉积来蚀刻层，同时保护下面的结构免受蚀刻。 在第三实施例中，使用单个掩模层的选择性沉积来将开口蚀刻到其中开口具有亚光刻直径的开口，即，开口的直径小于可以用特定光刻技术实现的开口的直径 雇用。

公开(公告)号：US08299455B2

公开(公告)日：2012-10-30

申请号：US11872291

申请日：2007-10-15

申请人： Bruce B. Doris ,  Carl J. Radens ,  Anthony K. Stamper ,  Jay W. Strane

发明人： Bruce B. Doris ,  Carl J. Radens ,  Anthony K. Stamper ,  Jay W. Strane

IPC分类号： H01L29/06

CPC分类号： H01L21/28518 ,  B81B2207/07 ,  B81C1/00095 ,  B81C2201/0149 ,  H01L21/3086 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.

摘要翻译： 自组装聚合物技术用于在存在于半导体结构的导电接触区域中的材料内形成至少一个有序的纳米尺度图案。 具有有序纳米尺寸图案的材料是场效应晶体管的互连结构或半导体源和漏极扩散区的导电材料。 在接触区域内有序的纳米尺寸图案材料的存在增加了用于随后的接触形成的总面积（即界面面积），这又降低了结构的接触电阻。 接触电阻的降低又改善了通过结构的电流的流动。 除了上述之外，本发明的方法和结构不影响结构的结电容，因为结面积保持不变。

公开(公告)号：US20120132966A1

公开(公告)日：2012-05-31

申请号：US11872291

申请日：2007-10-15

申请人： Bruce B. Doris ,  Carl J. Radens ,  Anthony K. Stamper ,  Jay W. Strane

发明人： Bruce B. Doris ,  Carl J. Radens ,  Anthony K. Stamper ,  Jay W. Strane

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/28518 ,  B81B2207/07 ,  B81C1/00095 ,  B81C2201/0149 ,  H01L21/3086 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.

摘要翻译： 自组装聚合物技术用于在存在于半导体结构的导电接触区域中的材料内形成至少一个有序的纳米尺度图案。 具有有序纳米尺寸图案的材料是场效应晶体管的互连结构或半导体源和漏极扩散区的导电材料。 在接触区域内有序的纳米尺寸图案材料的存在增加了用于随后的接触形成的总面积（即界面面积），这又降低了结构的接触电阻。 接触电阻的降低又改善了通过结构的电流的流动。 除了上述之外，本发明的方法和结构不影响结构的结电容，因为结面积保持不变。

公开(公告)号：US06960306B2

公开(公告)日：2005-11-01

申请号：US10207773

申请日：2002-07-31

申请人： Roy C. Iggulden ,  Padraic Shafer ,  Kwong Hon (Keith) Wong ,  Michael M. Iwatake ,  Jay W. Strane ,  Thomas Goebel ,  Donna D. Miura ,  Chet Dziobkowski ,  Werner Robl ,  Brian Hughes

发明人： Roy C. Iggulden ,  Padraic Shafer ,  Kwong Hon (Keith) Wong ,  Michael M. Iwatake ,  Jay W. Strane ,  Thomas Goebel ,  Donna D. Miura ,  Chet Dziobkowski ,  Werner Robl ,  Brian Hughes

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/32051 ,  H01L21/76838

摘要： In a method of fabricating a metallization structure during formation of a microelectronic device, the improvement of reducing metal shorts in blanket metal deposition layers later subjected to reactive ion etching, comprising: a) depositing on a first underlayer, a blanket of an aluminum compound containing an electrical short reducing amount of an alloy metal in electrical contact with the underlayer; b) depositing a photoresist and exposing and developing to leave patterns of photoresist on the blanket aluminum compound containing an electrical short reducing amount of an alloy metal; and c) reactive ion etching to obtain an aluminum compound containing an alloy metal line characterized by reduced shorts in amounts less than the aluminum compound without said short reducing amount of alloy metal.

摘要翻译： 在微电子器件形成期间制造金属化结构的方法中，改进后续进行反应离子蚀刻的覆盖金属沉积层中的金属短路，包括：a）沉积在第一底层上， 与底层电接触的合金金属的电短路减少量; b）沉积光致抗蚀剂并曝光和显影以在包含合金金属的电短缩量的橡皮布铝化合物上留下光刻胶图案; 和c）反应离子蚀刻，以获得含有合金金属线的铝化合物，其特征在于少于铝化合物的短路量，而没有所述合金金属的减少量。

公开(公告)号：US20120208332A1

公开(公告)日：2012-08-16

申请号：US13454709

申请日：2012-04-24

申请人： Bruce B. Doris ,  Carl J. Radens ,  Anthony K. Stamper ,  Jay W. Strane

发明人： Bruce B. Doris ,  Carl J. Radens ,  Anthony K. Stamper ,  Jay W. Strane

IPC分类号： H01L21/336

CPC分类号： H01L21/28518 ,  B81B2207/07 ,  B81C1/00095 ,  B81C2201/0149 ,  H01L21/3086 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.

公开(公告)号：US20080173942A1

公开(公告)日：2008-07-24

申请号：US11625431

申请日：2007-01-22

申请人： Huilong Zhu ,  Siddhartha Panda ,  Jay W. Strane ,  Sey-Ping Sun ,  Brian L. Tessier

发明人： Huilong Zhu ,  Siddhartha Panda ,  Jay W. Strane ,  Sey-Ping Sun ,  Brian L. Tessier

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A stressed semiconductor structure including at least one FinFET device on a surface of a substrate, typically a buried insulating layer of an initial semiconductor-on-insulator substrate, is provided. In a preferred embodiment, the at least one FinFET device includes a semiconductor Fin that is located on an unetched portion of the buried insulator layer which has a raised height as compared to an adjacent and adjoining etched portion of the buried insulating layer. The semiconductor Fin includes a gate dielectric on its sidewalls and optionally a hard mask located on an upper surface thereof. The inventive structure also includes a gate conductor, which is located on the surface of the substrate, typically the buried insulating layer, and the gate conductor is at least laterally adjacent to the gate dielectric located on the sidewalls of the semiconductor Fin. A stressed silicide is located on the gate conductor, which introduces stress into the channel of the FinFET device. The stressed silicide memorizes the stress from a sacrificial stressed film that is formed prior to forming the stressed silicide. The stress type of the stressed film is introduced into the silicide during a silicide anneal step.

摘要翻译： 提供了一种应力半导体结构，其包括在衬底的表面上的至少一个FinFET器件，通常是初始绝缘体上半导体衬底的掩埋绝缘层。 在优选实施例中，所述至少一个FinFET器件包括位于所述掩埋绝缘体层的未蚀刻部分上的半导体Fin，所述半导体Fin与所述掩埋绝缘层的相邻和相邻蚀刻部分相比具有升高的高度。 半导体鳍包括其侧壁上的栅极电介质和任选地位于其上表面上的硬掩模。 本发明的结构还包括栅极导体，其位于衬底的表面上，通常为掩埋绝缘层，并且栅极导体至少横向邻近位于半导体Fin的侧壁上的栅极电介质。 应力硅化物位于栅极导体上，其将应力引入FinFET器件的沟道中。 应力硅化物记忆在形成应力硅化物之前形成的牺牲应力膜的应力。 在硅化物退火步骤期间，将应力膜的应力类型引入到硅化物中。

公开(公告)号：US08421077B2

公开(公告)日：2013-04-16

申请号：US12795973

申请日：2010-06-08

申请人： Sameer H. Jain ,  Carl J. Radens ,  Shahab Siddiqui ,  Jay W. Strane

发明人： Sameer H. Jain ,  Carl J. Radens ,  Shahab Siddiqui ,  Jay W. Strane

IPC分类号： H01L29/10

CPC分类号： H01L29/7833 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659

摘要： A replacement gate field effect transistor includes at least one self-aligned contact that overlies a portion of a dielectric gate cap. A replacement gate stack is formed in a cavity formed by removal of a disposable gate stack. The replacement gate stack is subsequently recessed, and a dielectric gate cap having sidewalls that are vertically coincident with outer sidewalls of the gate spacer is formed by filling the recess over the replacement gate stack. An anisotropic etch removes the dielectric material of the planarization layer selective to the material of the dielectric gate cap, thereby forming at least one via cavity having sidewalls that coincide with a portion of the sidewalls of the gate spacer. A portion of each diffusion contact formed by filling the at least one via cavity overlies a portion of the gate spacer and protrudes into the dielectric gate cap.

摘要翻译： 替代栅极场效应晶体管包括至少一个自对准接触，其覆盖在电介质栅极盖的一部分上。 在通过去除一次性栅极堆叠而形成的空腔中形成替换栅极堆叠。 替换栅极堆叠随后被凹入，并且具有与栅极间隔物的外侧壁垂直重合的侧壁的电介质栅极盖通过在该替代栅极叠层上填充该凹槽来形成。 各向异性蚀刻去除对介电栅极盖的材料有选择性的平坦化层的电介质材料，从而形成具有与栅极间隔物的侧壁的一部分重合的侧壁的至少一个通孔。 通过填充至少一个通孔形成的每个扩散接触部分覆盖在栅极间隔物的一部分上并且突出到电介质栅极帽中。

公开(公告)号：US08188574B2

公开(公告)日：2012-05-29

申请号：US12704567

申请日：2010-02-12

申请人： Matthew S. Angyal ,  Mahender Kumar ,  Effendi Leobandung ,  Jay W. Strane

发明人： Matthew S. Angyal ,  Mahender Kumar ,  Effendi Leobandung ,  Jay W. Strane

IPC分类号： H01L29/72

CPC分类号： H01L23/585 ,  H01L21/76264 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip. A continuous metal ring extending continuously in the first lateral directions can surround the active portion of the chip, such metal ring connecting the GR contact ring with the first crack stop ring such that the metal line and the GR contact ring form a continuous seal preventing mobile ions from moving between the peripheral and active portions of the chip.

摘要翻译： 微电子元件，例如具有通过掩埋氧化物（BOX）层与大块单晶硅层分离的绝缘体上硅层（“SOI层”）的半导体芯片，其中裂纹阻挡层在第一横向至少延伸至少 通常平行于芯片的边缘以限定将芯片内的芯片的有源部分与芯片的周边部分分开的环状势垒。 裂纹停止件可以包括与BOX层上方的芯片的硅部分接触的第一裂纹阻挡环; 第一裂纹阻挡环可以在第一横向方向上连续延伸以围绕芯片的有效部分。 包括GR接触环的保护环（“GR”）可以向下延伸穿过SOI层和BOX层以导电接触大块单晶硅区域，GR接触环至少大致平行于第一裂纹阻挡环延伸以包围 芯片的有效部分。 在第一横向方向上连续延伸的连续金属环可以围绕芯片的有效部分，这种金属环将GR接触环与第一裂纹阻止环连接，使得金属线和GR接触环形成连续的密封，防止移动 离子在芯片的外围和有源部分之间移动。