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    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20160322303A1

    公开(公告)日：2016-11-03

    申请号：US15210623

    申请日：2016-07-14

    申请人： Semiconductor Manufacturing International (Shanghai) Corporation

    发明人： GUANGCAI FU ,  TIANLUN YANG ,  XIAOPING ZHANG

    IPC分类号： H01L23/528 ,  H01L21/02 ,  B81C1/00 ,  B81B7/00 ,  H01L29/06 ,  H01L23/532

    CPC分类号： H01L23/5283 ,  B81B7/007 ,  B81B2201/0264 ,  B81B2207/07 ,  B81C1/00095 ,  B81C1/00849 ,  B81C2201/0132 ,  H01L21/02068 ,  H01L21/475 ,  H01L23/53219 ,  H01L23/53233 ,  H01L23/53247 ,  H01L29/0649 ,  H01L2221/1063

    摘要： Semiconductor devices and fabrication methods are provided. In a semiconductor device, a semiconductor substrate includes a first electrode layer having a top surface coplanar with a top surface of the semiconductor substrate. A sacrificial layer is formed on the semiconductor substrate and the first electrode layer. A first mask layer made of a conductive material is formed on the sacrificial layer. The first mask layer and the sacrificial layer are etched until a surface of the first electrode layer is exposed to form openings through the first mask layer and the sacrificial layer. A cleaning process is performed to remove etch byproducts adhered to a surface of the first mask layer and adhered to sidewalls and bottom surfaces of the openings. Conductive plugs are formed in the openings after the cleaning process.

    摘要翻译： 提供了半导体器件和制造方法。 在半导体器件中，半导体衬底包括具有与半导体衬底的顶表面共面的顶表面的第一电极层。 在半导体衬底和第一电极层上形成牺牲层。 在牺牲层上形成由导电材料制成的第一掩模层。 蚀刻第一掩模层和牺牲层直到暴露第一​​电极层的表面以形成穿过第一掩模层和牺牲层的开口。 执行清洁处理以去除粘附到第一掩模层的表面并附着到开口的侧壁和底表面上的蚀刻副产物。 在清洁过程之后，在开口中形成导电塞。

    ELECTRICAL CONTACT
    3.
    发明申请
    ELECTRICAL CONTACT 审中-公开
    电气联系

    公开(公告)号：US20160293722A1

    公开(公告)日：2016-10-06

    申请号：US15038035

    申请日：2014-11-19

    申请人： NATIONAL UNIVERSITY OF SINGAPORE

    发明人： Christian Albertus NIJHUIS ,  Albert WAN ,  Li JIANG ,  Suchand Sangeeth CHANDRAMATHI SUKUMARAN

    IPC分类号： H01L29/45 ,  B32B15/04 ,  H01L51/10

    CPC分类号： H01L29/45 ,  B01L3/502707 ,  B01L3/502715 ,  B01L2300/0645 ,  B01L2300/0816 ,  B01L2400/0415 ,  B32B15/04 ,  B32B2307/202 ,  B32B2307/412 ,  B81B2201/058 ,  B81B2207/07 ,  B81C1/00095 ,  G01N27/44791 ,  H01L51/105

    摘要： The present invention relates to an electrical contact. In particular, it relates to an electrical contact capable of establishing an electrical contact with a soft material. More particular, the electrical contact comprises (a) a non-Newtonian liquid metal alloy, the non-Newtonian liquid metal alloy is formed in a polymer insulator, wherein the contact surface of the electrical contact that contacts the soft material is a smooth flat non-patterned surface, the surface comprising the non-Newtonian liquid metal alloy sandwiched between the polymer insulator. The microfluidic device comprising the electrical contact and a method for forming the electrical contact are also disclosed.

    摘要翻译： 本发明涉及电触点。 特别地，它涉及能够与软材料建立电接触的电接触。 更具体地说，电触点包括（a）非牛顿液态金属合金，非牛顿液态金属合金形成在聚合物绝缘体中，其中接触柔软材料的电触点的接触表面是光滑的平面非金属， 表面包括夹在聚合物绝缘体之间的非牛顿液态金属合金的表面。 还公开了包括电触点的微流体装置和用于形成电触点的方法。

    RF MEMS ELECTRODES WITH LIMITED GRAIN GROWTH
    4.
    发明申请
    RF MEMS ELECTRODES WITH LIMITED GRAIN GROWTH 审中-公开
    具有有限晶粒生长的RF MEMS电极

    公开(公告)号：US20160200565A1

    公开(公告)日：2016-07-14

    申请号：US14914071

    申请日：2014-08-27

    申请人： CAVENDISH KINETICS, INC

    发明人： Mickael RENAULT

    IPC分类号： B81B7/00 ,  B81C1/00 ,  H01G5/18 ,  B81B3/00

    CPC分类号： B81B7/0006 ,  B81B3/0078 ,  B81B2201/0221 ,  B81C1/00095 ,  B81C1/00341 ,  H01G5/18 ,  H01H1/0036 ,  H01H59/0009 ,  H01H2001/0052 ,  H01H2001/0084

    摘要： The present invention generally relates to an RF MEMS DVC and a method for manufacture thereof. To ensure that undesired grain growth does not occur and contribute to an uneven RF electrode, a multilayer stack comprising an AlCu layer and a layer containing titanium may be used. The titanium diffuses into the AlCu layer at higher temperatures such that the grain growth of the AlCu will be inhibited and the switching element can be fabricated with a consistent structure, which leads to a consistent, predictable capacitance during operation.

    摘要翻译： 本发明一般涉及RF MEMS DVC及其制造方法。 为了确保不发生不期望的晶粒生长并且有助于不均匀的RF电极，可以使用包括AlCu层和包含钛的层的多层堆叠。 钛在更高的温度下扩散到AlCu层中，使得AlCu的晶粒生长将被抑制，并且开关元件可以以一致的结构制造，这在操作期间导致一致的可预测的电容。

    Semiconductor device producing method
    5.
    发明授权
    Semiconductor device producing method 有权
    半导体器件制造方法

    公开(公告)号：US09349644B2

    公开(公告)日：2016-05-24

    申请号：US14424118

    申请日：2013-09-03

    申请人： DENSO CORPORATION

    发明人： Takashi Katsumata ,  Hisanori Yokura

    IPC分类号： H01L21/30 ,  H01L21/768 ,  H01L21/311 ,  B81C1/00 ,  H01L21/306 ,  H01L21/308

    CPC分类号： H01L21/76898 ,  B81C1/00095 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/0792 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/31144 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a method for producing a semiconductor device having a through electrode structure, a masking material is formed so as to bridge over a through hole formed in a second semiconductor substrate, and a hole is formed in the masking material at a position corresponding to the through hole. A contact hole is formed in an insulating film via this hole. In such a method, even if there is a large level difference from the surface of the second semiconductor substrate to the bottom of the through hole, only the masking material bridged over the through hole is exposed by photolithography. Therefore, photolithography for a large level difference is not necessary. As a result, the hole can be formed in the masking material successfully, and the contact hole can be formed successively by an anisotropic dry etching via this hole, even in the case where etching for a large level difference is performed.

    摘要翻译： 在具有贯通电极结构的半导体装置的制造方法中，形成遮蔽材料，以形成在第二半导体基板上形成的通孔上方，并且在掩模材料的与贯通电极对应的位置形成有孔 孔。 通过该孔在绝缘膜中形成接触孔。 在这种方法中，即使从第二半导体衬底的表面到通孔的底部存在较大的电平差，只有桥接在通孔上的掩模材料通过光刻曝光。 因此，不需要用于大电平差的光刻。 结果，可以成功地在掩模材料中形成孔，并且即使在进行大电平差的蚀刻的情况下，也可以通过该孔的各向异性干法蚀刻连续形成接触孔。

    Anisotropic conductor and method of fabrication thereof
    7.
    发明授权
    Anisotropic conductor and method of fabrication thereof 有权
    各向异性导体及其制造方法

    公开(公告)号：US09187314B2

    公开(公告)日：2015-11-17

    申请号：US14200991

    申请日：2014-03-07

    申请人： Robert Bosch GmbH

    发明人： Ando Lars Feyh ,  Fabian Purkl ,  Ashwin K. Samarao ,  Gary Yama ,  Gary O'Brien

    IPC分类号： H01L21/3205 ,  H01L23/52 ,  B81C1/00 ,  H01L21/314 ,  H01L21/02 ,  H01L45/00 ,  B82Y10/00 ,  B82Y30/00

    CPC分类号： B81C1/00095 ,  B81B7/0006 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/02601 ,  H01L21/3142 ,  H01L45/146

    摘要： An anisotropic conductor and a method of fabrication thereof. The anisotropic conductor includes an insulating matrix and a plurality of nanoparticles disposed therein. A first portion of the plurality of nanoparticles provides a conductor when subjected to a voltage and/or current pulse. A second portion of the plurality of the nanoparticles does not form a conductor when the voltage and or current pulse is applied to the first portion. The anisotropic conductor forms a conductive path between conductors of electronic devices, components, and systems, including microelectromechanical systems (MEMS) devices, components, and systems.

    摘要翻译： 各向异性导体及其制造方法。 各向异性导体包括绝缘基体和设置在其中的多个纳米颗粒。 多个纳米颗粒的第一部分在经受电压和/或电流脉冲时提供导体。 当电压和/或电流脉冲施加到第一部分时，多个纳米颗粒的第二部分不形成导体。 各向异性导体在电子器件，部件和系统的导体之间形成导电路径，包括微机电系统（MEMS）器件，部件和系统。

    METHOD FOR FORMING AN ELECTRICALLY CONDUCTIVE VIA IN A SUBSTRATE
    8.
    发明申请
    METHOD FOR FORMING AN ELECTRICALLY CONDUCTIVE VIA IN A SUBSTRATE 有权
    通过基板形成电导通的方法

    公开(公告)号：US20150262874A1

    公开(公告)日：2015-09-17

    申请号：US14440814

    申请日：2013-11-05

    申请人： MICRONIT MICROFLUIDICS B.V.

    发明人： Ronny Van'T Oever ,  Marko Theodoor Blom ,  Jeroen Haneveld ,  Johannes Oonk ,  Peter Tijssen

    IPC分类号： H01L21/768 ,  H01L23/498 ,  H01L21/48

    CPC分类号： H01L21/76879 ,  B81C1/00095 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The invention relates to a method for forming an electrically conductive via in a substrate and such a substrate comprising an electrically conductive, said method comprising the steps, to be performed in suitable sequence, of: a) providing a first substrate as said substrate; b) forming a through hole in said first substrate; c) providing a second substrate; d) bringing a first surface of said second substrate into contact with said first surface of said first substrate, such that said through hole in said first substrate is covered by said first surface of said second substrate; e) filling said through hole in said first substrate with an electrically conductive material by means of electroplating for forming said electrically conductive via, and f) removing said second substrate, wherein said first surface of said first substrate and said first surface of said second substrate each have a surface roughness R a of less than 2 nm, preferably less than 1 nm, more preferably less than 0.5 nm, and in that in step (d) said first surface of said first substrate and said first surface of said second substrate are brought in direct contact with each other, such that a direct bond is formed there between.

    摘要翻译： 本发明涉及一种用于在衬底中形成导电通孔的方法，并且这种衬底包括导电的所述方法，所述方法包括以适当顺序执行的以下步骤：a）提供作为所述衬底的第一衬底; b）在所述第一衬底中形成通孔; c）提供第二衬底; d）使所述第二基板的第一表面与所述第一基板的所述第一表面接触，使得所述第一基板中的所述通孔被所述第二基板的所述第一表面覆盖; e）通过用于形成所述导电通孔的电镀用导电材料填充所述第一衬底中的所述通孔，以及f）去除所述第二衬底，其中所述第一衬底的所述第一表面和所述第二衬底的所述第一表面 每个表面粗糙度R a小于2nm，优选小于1nm，更优选小于0.5nm，并且在步骤（d）中，所述第一衬底的所述第一表面和所述第二衬底的所述第一表面是 导致彼此直接接触，从而在其间形成直接粘结。

    Method of manufacturing through-glass vias
    9.
    发明授权
    Method of manufacturing through-glass vias 有权
    制造玻璃通孔的方法

    公开(公告)号：US09130016B2

    公开(公告)日：2015-09-08

    申请号：US13862953

    申请日：2013-04-15

    申请人： Schott Gemtron Corporation

    发明人： Eric H. Urruti

    IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48

    CPC分类号： H01L21/76802 ,  B81C1/00095 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a through-glass via hole involves providing a glass substrate having first and second substantially planar parallel surfaces; masking the first and second substantially planar parallel surfaces to form a via-patterned portion thereon; and etching the via-patterned portion on the first and second substantially planar parallel surfaces to form a first channel in the first substantially planar parallel surface and a second channel in the second substantially planar parallel surface. The first channel and second channel are substantially orthogonal or non-orthogonal to one another. The first channel and the second channel intersect to form a quadrilateral through-glass via hole having via openings at the first and second substantially planar parallel surfaces. A low cost, low complexity and high reliability method for producing a glass substrate having a plurality of through-glass via holes such that the glass substrate can be used, for example, as an interposer.

    摘要翻译： 形成贯通玻璃通孔的方法包括提供具有第一和第二基本上平面的平行表面的玻璃基板; 掩蔽第一和第二基本上平面的平行表面以在其上形成通孔图案部分; 以及蚀刻所述第一和第二基本上平面的平行表面上的通路图案部分，以在所述第一基本上平面的平行表面中形成第一通道，以及在所述第二基本上平面的平行表面中形成第二通道。 第一通道和第二通道彼此基本正交或非正交。 第一通道和第二通道相交以形成在第一和第二基本上平面的平行表面上具有通孔的四边形透玻璃通孔。 用于制造具有多个贯通玻璃通孔的玻璃基板的低成本，低复杂性和高可靠性的方法，使得可以使用例如玻璃基板作为插入件。

    Control circuitry routing configuration for MEMS devices
    10.
    发明授权
    Control circuitry routing configuration for MEMS devices 有权
    MEMS器件的控制电路布线配置

    公开(公告)号：US09090459B2

    公开(公告)日：2015-07-28

    申请号：US13689899

    申请日：2012-11-30

    申请人： HARRIS CORPORATION

    发明人： John E. Rogers

    IPC分类号： H02N1/00 ,  B81C1/00

    CPC分类号： B81C1/00182 ,  B81C1/00095

    摘要： A method for constructing a MEMS system includes first depositing on a surface of a substrate a first plurality of thin film layers formed of dielectric material. The first plurality of thin-film layers includes at least one conductive trace extending a distance on the substrate, parallel to the surface. A second plurality of layers is then deposited to form at least one MEMS device. The MEMS device is responsive to a control signal applied to a first input terminal and an electrical connection is formed from the conductive trace to the input terminal.

    摘要翻译： 一种用于构造MEMS系统的方法包括首先在基板的表面上沉积由电介质材料形成的第一多个薄膜层。 第一多个薄膜层包括至少一个导电迹线，该导电迹线在基板上延伸一定距离，平行于该表面。 然后沉积第二多个层以形成至少一个MEMS器件。 MEMS器件响应于施加到第一输入端子的控制信号，并且从导电迹线到输入端子形成电连接。