公开(公告)号：US07998786B2

公开(公告)日：2011-08-16

申请号：US12369839

申请日：2009-02-12

申请人： Je-Hun Lee ,  Jae-Kyeong Lee ,  Chang-Oh Jeong ,  Beom-Seok Cho

发明人： Je-Hun Lee ,  Jae-Kyeong Lee ,  Chang-Oh Jeong ,  Beom-Seok Cho

IPC分类号： H01L21/00

CPC分类号： H01L29/66765 ,  H01L27/12 ,  H01L29/458 ,  H01L29/4908

摘要： Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a molybdenum layer. An aluminum layer is deposited on the molybdenum layer. Another metal layer may be formed on the aluminum layer. The molybdenum layer has a face-centered cubic (FCC) lattice structure with a preferred orientation of (111).

摘要翻译： 在含有至少一个氧，氮和碳的前体气体的存在下，在基板上沉积钼以形成钼层，形成用于较大平板显示器的多层布线。 铝层沉积在钼层上。 可以在铝层上形成另一金属层。 钼层具有面心立方（FCC）晶格结构，其优选取向为（111）。

公开(公告)号：US20050285251A1

公开(公告)日：2005-12-29

申请号：US11049742

申请日：2005-02-04

申请人： Je-Hun Lee ,  Jae-Kyeong Lee ,  Chang-Oh Jeong ,  Beom-Seok Cho

发明人： Je-Hun Lee ,  Jae-Kyeong Lee ,  Chang-Oh Jeong ,  Beom-Seok Cho

IPC分类号： G02F1/1343 ,  G02F1/1345 ,  G02F1/136 ,  G02F1/1368 ,  G09F9/35 ,  H01L21/027 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/48 ,  H01L23/52 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L27/12 ,  H01L29/458 ,  H01L29/4908

摘要： Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a molybdenum layer. An aluminum layer is deposited on the molybdenum layer. Another metal layer may be formed on the aluminum layer. The molybdenum layer has a face-centered cubic (FCC) lattice structure with a preferred orientation of (111).

摘要翻译： 在含有至少一个氧，氮和碳的前体气体的存在下，在基板上沉积钼以形成钼层，形成用于较大平板显示器的多层布线。 铝层沉积在钼层上。 可以在铝层上形成另一金属层。 钼层具有面心立方（FCC）晶格结构，其优选取向为（111）。

公开(公告)号：US07511302B2

公开(公告)日：2009-03-31

申请号：US11049742

申请日：2005-02-04

申请人： Je-Hun Lee ,  Jae-Kyeong Lee ,  Chang-Oh Jeong ,  Beom-Seok Cho

发明人： Je-Hun Lee ,  Jae-Kyeong Lee ,  Chang-Oh Jeong ,  Beom-Seok Cho

IPC分类号： H01L27/14

CPC分类号： H01L29/66765 ,  H01L27/12 ,  H01L29/458 ,  H01L29/4908

摘要： Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a molybdenum layer. An aluminum layer is deposited on the molybdenum layer. Another metal layer may be formed on the aluminum layer. The molybdenum layer has a face-centered cubic (FCC) lattice structure with a preferred orientation of (111).

摘要翻译： 在含有至少一个氧，氮和碳的前体气体的存在下，在基板上沉积钼以形成钼层，形成用于较大平板显示器的多层布线。 铝层沉积在钼层上。 可以在铝层上形成另一金属层。 钼层具有面心立方（FCC）晶格结构，其优选取向为（111）。

公开(公告)号：US20070082434A1

公开(公告)日：2007-04-12

申请号：US11540131

申请日：2006-09-29

申请人： Yang-Ho Bae ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Beom-Seok Cho

发明人： Yang-Ho Bae ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Beom-Seok Cho

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： The present invention relates to a manufacturing method of a thin film transistor array panel. the method includes forming a gate line including a gate electrode on a substrate, forming a first insulating layer on the gate line, forming a semiconductor layer on the first insulating layer, forming an ohmic contact on the semiconductor layer, forming a data line including a source electrode and a drain electrode on the ohmic contact, depositing a second insulating layer, forming a first photoresist on the second insulating layer, etching the second insulating layer and the first insulating layer using the first photoresist as an etching mask to expose a portion of the drain electrode and a portion of the substrate, forming a pixel electrode connected to an exposed portion of the drain electrode using selective deposition, and removing the first photoresist.

摘要翻译： 本发明涉及薄膜晶体管阵列面板的制造方法。 该方法包括在基板上形成包括栅电极的栅极线，在栅极线上形成第一绝缘层，在第一绝缘层上形成半导体层，在半导体层上形成欧姆接触，形成数据线， 源电极和漏电极，沉积第二绝缘层，在第二绝缘层上形成第一光致抗蚀剂，使用第一光致抗蚀剂蚀刻第二绝缘层和第一绝缘层作为蚀刻掩模，以暴露部分 所述漏电极和所述衬底的一部分，使用选择性沉积形成连接到所述漏极的暴露部分的像素电极，以及去除所述第一光致抗蚀剂。

公开(公告)号：US08372701B2

公开(公告)日：2013-02-12

申请号：US12576217

申请日：2009-10-08

申请人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L21/00

CPC分类号： H01L27/1214 ,  H01L27/1225 ,  H01L27/124

摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

公开(公告)号：US08252639B2

公开(公告)日：2012-08-28

申请号：US12951981

申请日：2010-11-22

申请人： Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

发明人： Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

IPC分类号： H01L21/00

CPC分类号： H01L27/124 ,  H01L27/1288 ,  H01L29/12 ,  H01L29/458

摘要： The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.

摘要翻译： 本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在所述栅极绝缘层上且与所述栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地接触扩散阻挡层并面对栅电极上的源电极; 以及电连接到漏电极的像素电极。

公开(公告)号：US07352004B2

公开(公告)日：2008-04-01

申请号：US11249500

申请日：2005-10-14

申请人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L31/00

CPC分类号： H01L27/3279 ,  H01L27/124 ,  H01L27/1288 ,  H01L51/0023 ,  H01L51/56

摘要： The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.

摘要翻译： 本发明提供一种薄膜晶体管（TFT）阵列面板，其包括绝缘基板; 形成在所述绝缘基板上并具有含有Al的金属的第一层，比所述第一层更厚的含Cu金属的第二层的栅极线和栅电极; 栅极绝缘层，布置在栅极线上; 布置在栅绝缘层上的半导体; 数据线，其具有源电极并且布置在所述栅极绝缘层和所述半导体上; 布置在所述栅绝缘层和所述半导体上并面对所述源电极的漏电极; 钝化层，其具有接触孔并且布置在所述数据线和所述漏电极上; 以及设置在钝化层上并通过接触孔与漏电极耦合的像素电极。

公开(公告)号：US20060102907A1

公开(公告)日：2006-05-18

申请号：US11228852

申请日：2005-09-16

申请人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L29/04

CPC分类号： H01L27/1214 ,  H01L27/1225 ,  H01L27/124

摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

摘要翻译： 本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。

公开(公告)号：US07662715B2

公开(公告)日：2010-02-16

申请号：US11944083

申请日：2007-11-21

申请人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

发明人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

IPC分类号： H01L21/44

CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/3276 ,  Y10S438/924

摘要： The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.

摘要翻译： 本发明提供一种TFT阵列面板及其制造方法，其特征在于，具有含有Al的金属的下层和包含钼（Mo）的钼合金（Mo合金）的上层的信号线，至少包括 铌（Nb），钒（V）和钛（Ti）之一。 因此，防止在蚀刻工艺中可能出现的底切，突出和小鼠咬合，并且提供具有低电阻率和良好接触特性的信号线的TFT阵列面板。

公开(公告)号：US20080073674A1

公开(公告)日：2008-03-27

申请号：US11944130

申请日：2007-11-21

申请人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

发明人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

IPC分类号： H01L29/49

CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/3276 ,  Y10S438/924

摘要： The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.

摘要翻译： 本发明提供一种TFT阵列面板及其制造方法，其特征在于，具有含有Al的金属的下层和包含钼（Mo）的钼合金（Mo合金）的上层的信号线，至少包括 铌（Nb），钒（V）和钛（Ti）之一。 因此，防止在蚀刻工艺中可能出现的底切，突出和小鼠咬合，并且提供具有低电阻率和良好接触特性的信号线的TFT阵列面板。