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公开(公告)号：US06522269B2
公开(公告)日：2003-02-18
申请号：US09938082
申请日：2001-08-23
IPC分类号： H03M520
CPC分类号： H03M5/16
摘要： The system and method encodes a binary sequence of data bits into a sequence of ternary symbols and transmits the sequence of ternary symbols over a communication link. The encoding is performed so that no two consecutive symbols of the sequence are alike. The system and method assume that, for encoding, the previously encoded non-null symbol and the previously encoded symbol must be stored in a memory system. The sequence of symbols is transmitted in lieu of the binary sequence of data bits and decoded by a receiving device in order to restore the binary sequence of data bits from the received sequence of symbols. The decoding procedure assumes that three symbols must be received before a bit can be recovered. Hence, the system and method allow a self-delineation or self-sampling of a very-high speed data communication interface that is insensitive to large timing variations and skews.
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2.发明授权Decimation filter for a sigma-delta converter and data circuit terminating equipment including the same 失效Σ-Δ转换器的抽取滤波器和包括该Σ-Δ转换器的数据电路终端设备
公开(公告)号：US5329553A
公开(公告)日：1994-07-12
申请号：US878128
申请日：1992-05-04
CPC分类号： H03H17/0614 , H03H17/0664
摘要： A decimation filter for converting a received train of sigma-delta pulses in synchronism with a sigma-delta clock (fs) into a train of Pulse Code Modulation (PCM) samples having a PCM clock in accordance with the formula ##EQU1## includes a computer for computing one PCM sample from a sequence of sigma-delta samples in synchronism with the PCM clock and also a comparison circuit for determining whether phase correction of the PCM clock is necessary to lock the generation of the PCM samples on the sigma-delta clock extracted from the received sigma-delta signal, the decimation filter including shifters which shift the computation process at least one sigma-delta clock pulse in order to provide phase control in the generation of the PCM samples.
摘要翻译： 用于将接收到的Σ-Δ脉冲序列与Σ-Δ时钟（fs）同步转换成具有根据公式“IMAGE”的PCM时钟的脉冲编码调制（PCM）采样序列的抽取滤波器包括计算机 用于从与PCM时钟同步的一系列Σ-Δ样本计算一个PCM采样，并且还包括一个比较电路，用于确定PCM时钟的相位校正是否需要在提取的Σ-Δ时钟上锁定PCM采样的产生 从所接收的Σ-Δ信号中，抽取滤波器包括使运算处理至少一个Σ-Δ时钟脉冲移位的移位器，以便在生成PCM采样时提供相位控制。
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3.发明授权Decimation filter for a sigma-delta converter and A/D converter using the same 失效用于Σ-Δ转换器和使用其的A / D转换器的抽取滤波器
公开(公告)号：US5461641A
公开(公告)日：1995-10-24
申请号：US981157
申请日：1992-11-23
CPC分类号： H03H17/0664
摘要： A Decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of Pulse Coded Modulation (PCM) samples in accordance with the formula ##EQU1## where Cn is the sequence of the coefficients of the decimation filter which corresponds to a determined decimation factor, and the PCM samples being processed by a Digital Signal Processor (DSP). The decimation filter includes a device for storing a digital value representative of the DC component introduced during the sigma-delta coding process, with the digital value being computing by the DSP processor during an initialization phase. The decimation filter further includes a device operating after the latter initialization phase for subtracting the stored digital value from each of the PCM samples so that the resulting sequence of PCM samples appears free of any DC component introduced during the sigma-delta coding. This accurate DC component suppression is achieved without necessitating the use of additional digital signal processor resources from the processor. Preferably, the decimation filter comprises a device for detecting a saturation occurring in the computing of the PCM sample, and responsive to the saturation detection, for transmitting a predetermined PCM sample to the DSP processor.
摘要翻译： 一种抽取滤波器，用于根据与之对应的抽取滤波器的公式来将与Σ-Δ时钟（fs）同步的Σ-Δ脉冲序列转换成脉冲编码调制（PCM）采样序列 到确定的抽取因子，并且PCM采样由数字信号处理器（DSP）处理。 抽取滤波器包括用于存储代表在Σ-Δ编码处理期间引入的DC分量的数字值的装置，数字值由DSP处理器在初始化阶段期间计算。 抽取滤波器还包括在后一初始化阶段之后操作的装置，用于从每个PCM样本中减去所存储的数字值，使得所得到的PCM样本序列在Σ-Δ编码期间不会出现任何DC分量。 实现这种精确的DC分量抑制，而不需要使用来自处理器的附加数字信号处理器资源。 优选地，抽取滤波器包括用于检测在PCM采样的计算中出现的饱和度并且响应饱和检测用于将预定的PCM采样发送到DSP处理器的装置。
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4.发明授权Data circuit terminating equipment (DCE) including timing arrangements circuits controlled by processing means 失效数据电路终端设备（DCE），包括由处理装置控制的定时装置电路
公开(公告)号：US5315622A
公开(公告)日：1994-05-24
申请号：US754104
申请日：1991-09-03
CPC分类号： H04L27/24 , H04L27/00 , H04L7/0331
摘要： Data Circuit Terminating Equipment (DCE) allows the connection of a Data Terminal Equipment (DTE) to a telecommunication line. The DCE includes timing elements for providing the DTE with any desired transmitter signal element timing and any desired receiver signal element timing. The timing elements include processing elements for computing a sequence of digital values A(n) and for deriving therefrom a corresponding sequence of interrupt signals T(n). The receiver signal element timing, the transmitter signal element timing, the transmit sampling clock pulsing the D/A converter and the receive sampling clock pulsing the A/D converter are all controlled by different sequences of digital values computed by the processing elements. By generating appropriate sequences of digital values, the processing elements can provide any desired relationship between the different clocks to satisfy a transmit signal element timing slaved to the receiver signal element timing in synchronous mode, or on an external clock in tailing mode. The timing elements can also provide a transmit sampling clock slaved to the receive sampling clock in order to perform powerful digital echo cancellation techniques. Moreover, the processing elements can control the persistence of a received bit, which if a STOP bit, can allow the compensation of the DTE and the line data throughput difference.
摘要翻译： 数据电路终端设备（DCE）允许将数据终端设备（DTE）连接到电信线路。 DCE包括用于向DTE提供任何期望的发射机信号元素定时和任何期望的接收机信号元素定时的定时元件。 定时元件包括用于计算数字值A（n）的序列的处理元件，并由此导出相应的中断信号序列T（n）。 接收器信号元件定时，发送器信号元件定时，脉冲D / A转换器的发送采样时钟和脉冲A / D转换器的接收采样时钟都由处理元件计算的不同数字值序列控制。 通过产生数字值的适当序列，处理元件可以在不同时钟之间提供任何期望的关系，以满足在同步模式下或者在拖尾模式下的外部时钟在从属于接收机信号元件定时的发射信号元素定时。 定时元件还可以提供从属于接收采样时钟的发射采样时钟，以执行强大的数字回波消除技术。 此外，处理元件可以控制接收位的持续性，如果STOP位可以允许补偿DTE和线数据吞吐量差。
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5.发明授权
公开(公告)号：US5220327A
公开(公告)日：1993-06-15
申请号：US878106
申请日：1992-05-04
CPC分类号： H03H17/0614 , H03H17/0664
摘要： A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of PCM samples which includes counters (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta clock pulses, then decremented by two during N following sigma-delta clock pulses and then incremented again by one during N following sigma-delta clock pulses in order to provide a sequence of incrementation parameter DELTA(n). The decimation filter further includes storages (320, 330, 340) for storing the value of the coefficient C(n) corresponding to the decimation filter transfer function, and incrementers (327, 337, 347) driven by the sigma-delta clock fs for incrementing the storages with the incrementation parameter DELTA(n). Finally, the decimation filter includes computers (323, 333, 343, 327, 337, 347) for deriving from the contents C(n) of said storages and from the train of input sigma-delta samples S(i+n) one Pulse Code Modulation (PCM) sample every 3.times.N input sigma-delta samples according to the formula: ##EQU1##
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公开(公告)号：US4941151A
公开(公告)日：1990-07-10
申请号：US252303
申请日：1988-10-03
IPC分类号： H04L7/033
CPC分类号： H04L7/0331
摘要： A predictive clock extracting circuit having a first circuit for determining the duration between two consecutive transitions of a multilevel digital signal and a second circuit for generating an SPL pulse at half the duration after a third transition following on two consecutive previous transitions. A phase locked oscillator which is driven by said SPL pulse generates the extracted clock signal which is in phase with the SPL pulse and coincides with the center of the eye intervals of said multilevel digital signal. The system includes a first counter N which starts running in response to the detection of the first transition of the multilevel digital signal. The running stops when the second transition occurs. The result N(i) stored into the first counter N at second transition is therefore representative of the duration between the two consecutive first and second transitions. The preferred embodiment of the invention also involves an up/down counter K which generates a second counter K(i) that is expected to be representative of half the value of the first counter N(i). Counter K is adaptively updated by incrementing its current value K(i) by a fixed factor or, on the contrary, by decrementing its current value K(i) by a fixed damping factor.
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公开(公告)号：US06661786B1
公开(公告)日：2003-12-09
申请号：US09315446
申请日：1999-05-20
申请人： Jean-Claude Abbiate , Alain Blanc , Bernard Brezzo , Sylvie Gohl , Michel Poret
发明人： Jean-Claude Abbiate , Alain Blanc , Bernard Brezzo , Sylvie Gohl , Michel Poret
IPC分类号： H04L1250
CPC分类号： H04L49/1523 , H04L49/552
摘要： A service message system for a switching architecture including at least one Switch Fabric (10, 20) comprising a switch core (15, 25) located in a centralized building and a set of Switch Core Access Layer (SCAL) elements distributed in different physical areas for the attachment to the different Port adapters (30, 31). Each SCAL elements particularly includes a SCAL receive element (11-i) and a SCAL Xmit element (12-i) for the respective access to one input port and one output port via serial links. The service message is based on the use of a Cell qualifier field at the beginning of each cell, which comprises a first and a second field. The first field is the Filtering Control field which permits an easy decoding of a service message cell, when applicable. The second field is used for determining which particular type of service message is conveyed via the cell. Following the Cell qualifier is the Switch Routing Header (SRH) which permits the characterization of the destination of the cell and is used for controlling the routing process. Preferably, the service message is used in a fault tolerance configuration where two different Switch Fabrics act as a standby to each other and shares a part of the traffic. Each one is configured as a default routing path for some ports adapters and a backup path for the others. In that particular configuration, the service message system of the invention uses the first field of the Cell qualifier to transport a Direct filtering command causing the Switch fabric to route the cell when the SRH is representative of its default output port destination. Conversely, the first field may transport a Reverse filtering command in the first field that causes the Switch fabric to reverse the default routing process. The first field is also used for characterizing a service message cell which the second field indicates the accurate type. Particularly, two types are used for the production of the filling cells when no data cell is to be transmitted at a particular location of the switching architecture.
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8.发明授权Process for transporting a cell through a switching structure base on a single stage switch 失效通过单级开关上的开关结构基地传送电池的过程公开(公告)号：US06480501B1
公开(公告)日：2002-11-12
申请号：US09100903
申请日：1998-06-19
申请人： Alain Blanc , Jean-Claude Abbiate
发明人： Alain Blanc , Jean-Claude Abbiate
IPC分类号： H04L1254
CPC分类号： H04L12/5601 , H04L49/153 , H04L49/203 , H04L49/256 , H04L49/309 , H04L49/455
摘要： A process for transporting a data cell throughout a switch fabric having a centralized switching structure and a set of distributed, generally remotely located, Switch Core Access Layers (SCAL) permitting the attachment of the protocol adapters. Remotely with respect to the centralized switching structure, the data cell which is received from a telecommunications link is divided into k logical units (LUs) and additional bytes are introduced for permitting the reservation of a bitmap field that will be used for routing through the switch core. Every LU is coded in accordance with the 8B/10B coding process. Within the centralized switching structure, the k coded LUs are deserialized and the cell clock is obtained for each cell in order to reconstitute the data cell. In addition the routing byte reservations are filled with appropriate values (bit map) for the routing process within the switch by means of an access to an entry routing table. When the cell outputs the switching structure, a second access to a routing table permits the replacement of the previous bit map by new values in order to enhance multicast capabilities. The data cell is divided again in a set of k serialized logical units (LUs) in order to prepare a serialization through k links. The LUs are coded as previously to permit the merging of the LUs when different sets of switches operated in parallel are connected in a port expansion mode. Remotely with respect to the switch core, the coded LUs are deserialized and the data cell is reconstituted by means of the deserialization and extraction of the data cell clock transported by the 8B/10B coding process. The newly inserted values of the bit map are then used for enhancing multicasting capabilities.
摘要翻译： 一种用于在具有集中式交换结构的交换结构中传送数据单元的过程，以及允许协议适配器附接的分布式，通常位于远程位置的交换核心接入层（SCAL）。 远离集中式交换结构，从电信链路接收的数据信元被划分为k个逻辑单元（LU），并且引入附加字节以允许保留将用于通过交换机进行路由的位图字段 核心。 每个LU都按照8B / 10B编码过程进行编码。 在集中式交换结构中，k个编码的LU被反序列化，并且为每个小区获得单元时钟以便重构数据单元。 此外，通过对入口路由表的访问，路由字节预留用交换机内的路由进程的适当值（位图）填充。 当小区输出交换结构时，对路由表的第二次访问允许以先前的位图替换新的值，以便增强多播能力。 为了通过k个链路准备序列化，数据信元再次被划分成一组k个串行化的逻辑单元（LU）。 在以端口扩展模式连接不同组合的并行开关的情况下，逻辑单元按照以前的编码方式允许逻辑单元的合并。 相对于交换机核心，编码的LU被反序列化，并且数据信元通过由8B / 10B编码过程传输的数据信元时钟的反序列化和提取来重构。 然后，使用位图的新插入值来增强多播能力。
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公开(公告)号：US06563346B2
公开(公告)日：2003-05-13
申请号：US09683319
申请日：2001-12-13
IPC分类号： H03D300
CPC分类号： H03D13/003
摘要： A method and circuit for comparing the frequencies of two clocks (clock—1 and clock—2), without taking into account their phase, is disclosed. Each clock is associated to a circular counter (100-1 and 100-2) which are initialized to different values, and the contents of the circular counters are compared. When the frequencies of the two clocks (clock—1 and clock—2) are equal, both counters (100-1 and 100-2) are incremented at a common frequency and thus, due to the initialization conditions, the contents of both counters can never be equal. Conversely, when the frequencies of the two clocks are different, the counters (100-1 and 100-2) are not increased at a common frequency and thus, after several clock pulses, the contents of the counters are equal, indicating different clock frequencies. In a preferred embodiment, the circular counters (100-1 and 100-2) are 2-bit circular counters.
摘要翻译： 公开了一种用于比较两个时钟（时钟-1和时钟-2）的频率而不考虑它们的相位的方法和电路。 每个时钟与循环计数器（100-1和100-2）相关联，其被初始化为不同的值，并且比较圆形计数器的内容。 当两个时钟（时钟-1和时钟-2）的频率相等时，两个计数器（100-1和100-2）以公共频率递增，因此，由于初始化条件，两个计数器的内容 永远不能平等 相反，当两个时钟的频率不同时，计数器（100-1和100-2）不以共同频率增加，因此在几个时钟脉冲之后，计数器的内容相等，表示不同的时钟频率 。 在优选实施例中，循环计数器（100-1和100-2）是2位循环计数器。
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10.发明授权Method and apparatus for locating sampling points in a synchronous data stream 失效用于定位同步数据流中采样点的方法和装置公开(公告)号：US06795515B1
公开(公告)日：2004-09-21
申请号：US09547919
申请日：2000-04-11
IPC分类号： H03K19096
CPC分类号： H04L7/0338 , H04L7/046
摘要： An apparatus and process for updating a sample time in a serial link which converts serial data in parallel data. A delay line stores multiple samples of at least two data bits received over the serial link. The contents of the delay line are matched so that they can be analyzed by a processor to determine an optimum sampling position in the delay line. The processor is programmed to analyze contents of the latch by creating a sample mask from a plurality of delay line samples. The sample mask identifies transition edges of first and second data bits within the delay line. The transition edges are validated with respect to the presence, for first and second initial sampling positions for the respective data bits. New sampling positions are determined from the validated edges, and the initial sampling positions are updated with sampling positions which have been determined from the new sampling positions. In this way phase jitter induced by environmental concerns is minimized using new sampling positions along the delay line for coding the data into parallel data.
摘要翻译： 一种用于更新以并行数据转换串行数据的串行链路中的采样时间的装置和处理。 延迟线存储通过串行链路接收的至少两个数据位的多个样本。 延迟线的内容被匹配，使得它们可以被处理器分析以确定延迟线中的最佳采样位置。 处理器被编程为通过从多个延迟线样本中创建采样掩模来分析锁存器的内容。 采样掩码识别延迟线内的第一和第二数据位的转换边缘。 对于相应数据位的第一和第二初始采样位置的存在，过渡边缘被验证。 从验证的边缘确定新的采样位置，并且利用从新采样位置确定的采样位置更新初始采样位置。 以这种方式，使用沿着延迟线的新采样位置来最小化由环境问题引起的相位抖动，以将数据编码为并行数据。
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