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1.发明授权
公开(公告)号：US5220327A
公开(公告)日：1993-06-15
申请号：US878106
申请日：1992-05-04
CPC分类号： H03H17/0614 , H03H17/0664
摘要： A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of PCM samples which includes counters (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta clock pulses, then decremented by two during N following sigma-delta clock pulses and then incremented again by one during N following sigma-delta clock pulses in order to provide a sequence of incrementation parameter DELTA(n). The decimation filter further includes storages (320, 330, 340) for storing the value of the coefficient C(n) corresponding to the decimation filter transfer function, and incrementers (327, 337, 347) driven by the sigma-delta clock fs for incrementing the storages with the incrementation parameter DELTA(n). Finally, the decimation filter includes computers (323, 333, 343, 327, 337, 347) for deriving from the contents C(n) of said storages and from the train of input sigma-delta samples S(i+n) one Pulse Code Modulation (PCM) sample every 3.times.N input sigma-delta samples according to the formula: ##EQU1##
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2.发明授权Switching apparatus comprising a centralized switch core and at least one SCAL element(s) for the attachment of various protocol adapters 失效交换设备包括集中式交换机核心和至少一个用于附接各种协议适配器的SCAL元件公开(公告)号：US06728251B1
公开(公告)日：2004-04-27
申请号：US09315906
申请日：1999-05-20
申请人： Alain Blanc , Gerard Orengo , Michel Poret
发明人： Alain Blanc , Gerard Orengo , Michel Poret
IPC分类号： H04L1228
CPC分类号： H04L49/1538 , H04L49/30 , H04L49/3081 , H04L2012/5652 , H04L2012/5681 , H04Q11/0478
摘要： By appropriate arrangement of two sets of tables chosen to be complementary, cells which are conveyed through a first multiplexor, n RAM storages and the second are subject to a cell rearrange-ment enabling introduction of at least one bitmap field, thereby producing the n Logical Units. When two bytes which are processed in parallel have to be loaded at the same time in the same RAM storage, one particular byte is stored into one RAM available for a Write operation by use of the first set of tables, thereby causing an alteration to the normal association between the n RAMs and the n Logical Units which is then re-established by the second set of tables.
摘要翻译： 通过适当布置选择为互补的两组表，通过第一多路复用器传送的单元，n个RAM存储器和第二个存储单元进行单元重新布置，使得能够引入至少一个位图字段，从而产生n逻辑 单位。 当并行处理的两个字节必须同时被加载到同一个RAM存储器中时，通过使用第一组表，一个特定的字节被存储到可用于写入操作的一个RAM中，从而导致对 n个RAM和n个逻辑单元之间的正常关联，然后由第二组表重新建立。
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公开(公告)号：US5028925A
公开(公告)日：1991-07-02
申请号：US410166
申请日：1989-09-20
IPC分类号： H03M3/02
摘要： A sigma-delta converter including a switching component controlled by a first clock having determined transitions for generating a train of sigma-delta code pulses corresponding to an analog input value. The sigma-delta includes circuits for generating a second clock of a same frequency as the first clock and having a negative transition followed after a defined period of time (d2) by a positive transition. The determined transitions of the first clock controlling the switching element occur during said defined period of time. There is also included a circuit controlled by the sigma-delta code pulse train and said second clock for generating a train of sigma-delta pulses insensitive to the mismatch of the rise and fall times of the switching element thereby improving the linearity and the signal-to-noise ratio of the converter. The control of the period of time allows varying of the energy of the pulses in order to provide pulse trains which, when applied to a sigma-delta decoder, provide an analog output value representative of, but attenuated with respect to, the analog input value.
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4.发明授权
公开(公告)号：US5389838A
公开(公告)日：1995-02-14
申请号：US124739
申请日：1993-09-21
申请人： Gerard Orengo
发明人： Gerard Orengo
IPC分类号： G06F7/00 , G06F1/04 , H03K19/00 , H03K19/173
CPC分类号： G06F1/04
摘要： A finite state machine connected to a plurality of units which enables to manage the execution of M asynchronous signals to select one of these M asynchronous signals which may become a user clock at a moment which is independent from the pulse of the state machine clock within a minimum of time. The state machine comprises a combinational logic circuit (1) receiving a set of primary input signals (3) which contains N asynchronous input signals and outputting state variable output signals (6) to a state variable register (2). The register (2) is driven by a clock signal (7) which is the clock signal of the state machine and provides M state variable register output signals (51, 52) to M additional latches (10, 20) which delay the signal until they receive a timing pulse (71 or 72) from the combinational circuit. The moment when a pulse is generated is defined by one of the M equations determined by a particular need whose requirements are inputted among the set of primary input signals (3) in the combinational circuit, the equation may also depend on the variable which indicates the signal selected by means of line (50) looping back to combinational logic circuit so that said state machine may be used as a clock select selecting one of the clock input signal to become a user clock; and each time an equation is satisfied, the combinational circuit generates a timing pulse to the corresponding latch which generates then an output signal (53 or 54) to the different units and also to the combinational circuit to indicate the present state of the state machine. Those output signals (53, 54) may be used in connection with a selection means (110) to select which clock input signal is to become a user clock.
摘要翻译： 连接到多个单元的有限状态机，其能够管理M个异步信号的执行，以选择这些M个异步信号中的一个，这些异步信号可能在与时钟内的状态机时钟的脉冲无关的时刻成为用户时钟 最短的时间。 状态机包括组合逻辑电路（1），接收一组包含N个异步输入信号的主输入信号（3），并将状态变量输出信号（6）输出到状态变量寄存器（2）。 寄存器（2）由时钟信号（7）驱动，时钟信号（7）是状态机的时钟信号，并向M个附加锁存器（10,20）提供M个可变寄存器输出信号（51,52），延迟信号直到 它们从组合电路接收定时脉冲（71或72）。 产生脉冲的时刻由组合电路中的一组主要输入信号（3）中由特定需要确定的M个方程中的一个定义，该方程式还可以取决于指示 通过线路（50）选择的信号循环回组合逻辑电路，使得所述状态机可以用作选择时钟输入信号之一以成为用户时钟的时钟选择; 并且每当满足等式时，组合电路产生到相应的锁存器的定时脉冲，其产生到不同单元的输出信号（53或54），并且还产生组合电路以指示状态机的当前状态。 这些输出信号（53,54）可以与选择装置（110）一起使用，以选择哪个时钟输入信号将成为用户时钟。
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公开(公告)号：US4972360A
公开(公告)日：1990-11-20
申请号：US396580
申请日：1989-08-21
申请人： Maurice Cukier , Daniel Mauduit , Gerard Orengo
发明人： Maurice Cukier , Daniel Mauduit , Gerard Orengo
CPC分类号： H03H17/0628 , H04L7/033
摘要： Digital filter used in a sigma-delta decoder wherein each input sample is involved in the computation of three consecutive pulse coded modulation (PCM) output samples. During one sigma-delta sampling period, the filter performs three parallel operations by multiplexing one adder running three times faster than the sigma-delta clock for loading one of three accumulators. As the analog-to-digital converter must be kept in phase with remote modem transmit clock, the PCM sampling clock is controlled by the phase tracking performed by adding or subtracting one period of the crystal oscillator from time to time to the PCM sampling clock period. Rotating the order in which the accumulators are loaded by the adder each PCM sampling time enables having zero as the last coefficient value to add to the accumulator, the contents of which is used as PCM output samples. Thus, each PCM sample value is available in the corresponding accumulator one sigma-delta clock period before the last computation. In case of a correction which shortens or lengthens the PCM sampling period, this correction does not change the PCM sample value to be output since the last computation which is either cancelled or repeated, consists in adding zero to the previous accumulator contents.
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公开(公告)号：US4482815A
公开(公告)日：1984-11-13
申请号：US464542
申请日：1983-02-07
申请人： Gerard Orengo
发明人： Gerard Orengo
CPC分类号： G05F1/585 , Y10T307/505 , Y10T307/615
摘要： A back-up voltage source useful over a comparatively long time interval during a power outage or voltage fluctuation is described. A circuit for adjusting the position of a voltage difference available at the back-up supply outputs is described. A potential difference appearing at the terminals of a floating voltage source is connected to a reference circuit for generating a voltage reference from the difference of potential. A voltage follower connected to the reference and to a second voltage source is employed to cause the voltage follower to reposition the potential difference of the supply so as to force the voltage reference to a level equal to the second voltage source.
摘要翻译： 描述了在断电或电压波动期间在相当长的时间间隔内有用的备用电压源。 描述用于调整在备用电源输出端可用的电压差的位置的电路。 出现在浮动电压源的端子处的电位差连接到用于从电位差产生电压基准的参考电路。 连接到基准电压源和第二电压源的电压跟随器用于使电压跟随器重新定位电源的电位差，以将电压基准强制到等于第二电压源的电平。
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公开(公告)号：US4446385A
公开(公告)日：1984-05-01
申请号：US327865
申请日：1981-12-07
申请人： Gerard Orengo , Michel Verhaeghe
发明人： Gerard Orengo , Michel Verhaeghe
IPC分类号： G01R19/165 , H03F3/45 , H03K5/08 , H03K5/24
CPC分类号： H03K5/2418 , H03F3/4508 , H03F3/45484
摘要： A voltage comparator circuit with a wide common mode input voltage range which extends beyond supply voltage parameter values. The comparator circuit utilizes an input stage having two input transistors, the emitter electrodes of which are connected to receive input signals and the collector electrodes of which are connected to two current sources. A current fixing circuit is coupled to the collector electrodes of said two input transistors and acts to fix the direct current in the collector circuits at a first value IO and the currents supplied by the current sources at a second value k IO, where k is greater than 2. An output stage is provided with two input circuits respectively connected to the collector electrodes of the two input transistors and with a logic circuit arrangement set to either one of two logic levels in accordance with the sign of the difference in the voltages applied to the pair of emitter electrodes of the two input transistors.
摘要翻译： 具有宽泛共模输入电压范围的电压比较器电路，其延伸超出电源电压参数值。 比较器电路使用具有两个输入晶体管的输入级，其输入电极连接以接收输入信号，并且其集电极连接到两个电流源。 电流固定电路耦合到所述两个输入晶体管的集电极，用于将集电极电路中的直流电流固定在第一值IO和电流源提供的电流为第二值k IO，其中k大于 输出级设置有分别连接到两个输入晶体管的集电极的两个输入电路，并且逻辑电路装置根据施加到...的电压差的符号设置为两个逻辑电平中的任一个 两个输入晶体管的一对发射极。
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公开(公告)号：US4412335A
公开(公告)日：1983-10-25
申请号：US305564
申请日：1981-09-25
IPC分类号： H03K5/04 , G06F1/10 , H03K5/1252 , H04L7/00 , H04L7/04 , H04L25/20 , H04L25/40 , H04L25/52 , H03K6/02
CPC分类号： H03K5/1252 , H04L25/20 , H04L7/00
摘要： A digital signal distribution system for distributing digital signals to remote points of a machine. It is comprised of a distribution device arranged at each of said points. In each device, a receiver receives on its true and complementary inputs, the signal to be distributed. The drivers are connected to the receivers through a crossed connection, the true output of the receiver being connected to the complementary input of the driver, and the complementary output of the receiver being connected to the true input of the driver, so as to cancel the skew of the pulse width of the signal to be distributed. The signals on outputs of the driver circuits can be utilized locally or transmitted to another remote point.
摘要翻译： 一种用于将数字信号分配到机器的远程点的数字信号分配系统。 它由布置在每个所述点上的分配装置组成。 在每个设备中，接收机接收其真实和互补的输入信号，以分配信号。 驱动器通过交叉连接连接到接收器，接收器的真实输出连接到驱动器的互补输入，并且接收器的互补输出连接到驱动器的真实输入，以便取消 要分配的信号的脉冲宽度偏移。 驱动器电路的输出信号可以在本地使用或传输到另一个远程点。
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