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    METHODS AND APPARATUS OF FLUORINE PASSIVATION
    1.
    发明申请
    METHODS AND APPARATUS OF FLUORINE PASSIVATION 有权
    氟化物的方法与装置

    公开(公告)号：US20110169104A1

    公开(公告)日：2011-07-14

    申请号：US12687574

    申请日：2010-01-14

    申请人： Jeff J. Xu ,  Liang-Gi Yao ,  Ta-Ming Kuan

    发明人： Jeff J. Xu ,  Liang-Gi Yao ,  Ta-Ming Kuan

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L21/2822 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

    摘要： The present disclosure provides methods and apparatus of fluorine passivation in IC device fabrication. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate and passivating a surface of the substrate with a mixture of hydrofluoric acid and alcohol to form a fluorine-passivated surface. The method further includes forming a gate dielectric layer over the fluorine-passivated surface, and then forming a metal gate electrode over the gate dielectric layer. A semiconductor device fabricated by such a method is also disclosed.

    摘要翻译： 本公开提供了IC器件制造中氟钝化的方法和装置。 在一个实施例中，制造半导体器件的方法包括提供衬底并用氢氟酸和醇的混合物钝化衬底的表面以形成氟钝化表面。 该方法还包括在氟钝化表面上形成栅极电介质层，然后在栅极介电层上形成金属栅电极。 还公开了通过这种方法制造的半导体器件。

    Methods and apparatus of fluorine passivation
    2.
    发明授权
    Methods and apparatus of fluorine passivation 有权
    氟钝化的方法和装置

    公开(公告)号：US08106469B2

    公开(公告)日：2012-01-31

    申请号：US12687574

    申请日：2010-01-14

    申请人： Jeff J. Xu ,  Liang-Gi Yao ,  Ta-Ming Kuan

    发明人： Jeff J. Xu ,  Liang-Gi Yao ,  Ta-Ming Kuan

    IPC分类号： H01L21/02

    CPC分类号： H01L21/2822 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

    摘要： The present disclosure provides methods and apparatus of fluorine passivation in IC device fabrication. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate and passivating a surface of the substrate with a mixture of hydrofluoric acid and alcohol to form a fluorine-passivated surface. The method further includes forming a gate dielectric layer over the fluorine-passivated surface, and then forming a metal gate electrode over the gate dielectric layer. A semiconductor device fabricated by such a method is also disclosed.

    摘要翻译： 本公开提供了IC器件制造中氟钝化的方法和装置。 在一个实施例中，制造半导体器件的方法包括提供衬底并用氢氟酸和醇的混合物钝化衬底的表面以形成氟钝化表面。 该方法还包括在氟钝化表面上形成栅极电介质层，然后在栅极介电层上形成金属栅电极。 还公开了通过这种方法制造的半导体器件。

    Metal stress memorization technology
    4.
    发明授权
    Metal stress memorization technology 有权
    金属应力记忆技术

    公开(公告)号：US07985652B2

    公开(公告)日：2011-07-26

    申请号：US11855701

    申请日：2007-09-14

    申请人： Chung-Hu Ke ,  Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

    发明人： Chung-Hu Ke ,  Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L29/665 ,  H01L29/7847

    摘要： A semiconductor device and method for manufacturing a tensile strained NMOS and a compressive strained PMOS transistor pair, wherein a stressor material is sacrificial is disclosed. The method provides for a substrate, which includes a source/drain for an NMOS transistor, and a PMOS transistor. A first barrier layer is formed on the substrate and a first stressor material is formed on the first barrier layer. The first barrier layer is selectively removed from the PMOS transistor. The substrate is flash annealed and the remaining first stressor material and barrier layer is removed from the substrate.

    摘要翻译： 公开了用于制造拉伸应变NMOS和压缩应变PMOS晶体管对的半导体器件和方法，其中应力源材料是牺牲的。 该方法提供了一种衬底，其包括用于NMOS晶体管的源极/漏极和PMOS晶体管。 在基板上形成第一阻挡层，在第一阻挡层上形成第一应力源材料。 从PMOS晶体管选择性地去除第一势垒层。 衬底被闪光退火，剩余的第一应力材料和阻挡层从衬底上去除。

    Semiconductor Device With Localized Stressor
    6.
    发明申请
    Semiconductor Device With Localized Stressor 有权
    具有局部应力的半导体器件

    公开(公告)号：US20100330755A1

    公开(公告)日：2010-12-30

    申请号：US12873889

    申请日：2010-09-01

    申请人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

    发明人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

    摘要翻译： 提供具有局部应力源的诸如PMOS晶体管的半导体器件。 凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。 这些凹部填充有应力诱导层。 去除虚拟凹槽并形成轻掺杂的排水沟。 此后，形成新的间隔物并且应力诱导层凹陷。 可以执行一个或多个附加植入物以完成源极/漏极区域。 在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。 也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

    Metal Stress Memorization Technology
    7.
    发明申请
    Metal Stress Memorization Technology 有权
    金属应力记忆技术

    公开(公告)号：US20090075442A1

    公开(公告)日：2009-03-19

    申请号：US11855701

    申请日：2007-09-14

    申请人： Chung-Hu Ke ,  Ta-Ming Kuan ,  Chih-Hsin Ho ,  Wen-Chin Lee

    发明人： Chung-Hu Ke ,  Ta-Ming Kuan ,  Chih-Hsin Ho ,  Wen-Chin Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L29/665 ,  H01L29/7847

    摘要： A semiconductor device and method for manufacturing a tensile strained NMOS and a compressive strained PMOS transistor pair, wherein a stressor material is sacrificial is disclosed. The method provides for a substrate, which includes a source/drain for an NMOS transistor, and a PMOS transistor. A first barrier layer is formed on the substrate and a first stressor material is formed on the first barrier layer. The first barrier layer is selectively removed from the PMOS transistor. The substrate is flash annealed and the remaining first stressor material and barrier layer is removed from the substrate.

    摘要翻译： 公开了用于制造拉伸应变NMOS和压缩应变PMOS晶体管对的半导体器件和方法，其中应力源材料是牺牲的。 该方法提供了一种衬底，其包括用于NMOS晶体管的源极/漏极和PMOS晶体管。 在基板上形成第一阻挡层，在第一阻挡层上形成第一应力源材料。 从PMOS晶体管选择性地去除第一势垒层。 衬底被闪光退火，剩余的第一应力材料和阻挡层从衬底上去除。

    Semiconductor Device with Localized Stressor
    8.
    发明申请
    Semiconductor Device with Localized Stressor 有权
    具有局部应力的半导体器件

    公开(公告)号：US20080258233A1

    公开(公告)日：2008-10-23

    申请号：US11738968

    申请日：2007-04-23

    申请人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

    发明人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

    IPC分类号： H01L29/76

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

    摘要翻译： 提供具有局部应力源的诸如PMOS晶体管的半导体器件。 凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。 这些凹部填充有应力诱导层。 去除虚拟凹槽并形成轻掺杂的排水沟。 此后，形成新的间隔物并且应力诱导层凹陷。 可以执行一个或多个附加植入物以完成源极/漏极区域。 在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。 也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

    Methods for forming a transistor with a strained channel
    10.
    发明授权
    Methods for forming a transistor with a strained channel 有权
    用于形成具有应变通道的晶体管的方法

    公开(公告)号：US08236658B2

    公开(公告)日：2012-08-07

    申请号：US12477757

    申请日：2009-06-03

    申请人： Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

    发明人： Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

    摘要： A semiconductor device and method for fabricating a semiconductor device providing reduced short channel effects is disclosed. The method comprises providing a substrate comprising a first material; forming at least one gate stack over the substrate; forming one or more recesses in the substrate, wherein the one or more recesses define at least one source region and at least one drain region; and forming a pocket, a first layer comprising a second material, and a second layer comprising a third material in the one or more recesses, the pocket being disposed between the first layer and the substrate.

    摘要翻译： 公开了一种用于制造提供减小的短通道效应的半导体器件的半导体器件和方法。 该方法包括提供包括第一材料的基底; 在所述衬底上形成至少一个栅极堆叠; 在所述衬底中形成一个或多个凹槽，其中所述一个或多个凹部限定至少一个源极区域和至少一个漏极区域; 并且形成袋，包含第二材料的第一层和在所述一个或多个凹部中包含第三材料的第二层，所述袋设置在所述第一层和所述基底之间。