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公开(公告)号：US06445624B1
公开(公告)日：2002-09-03
申请号：US09790538
申请日：2001-02-23
IPC分类号： G11C700
CPC分类号： G11C7/1066 , G06F13/1689 , G06F13/4243 , G11C7/1006 , G11C7/1072 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/409 , G11C2207/107 , G11C2207/2254 , G11C2207/2281
摘要： The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.
摘要翻译： 通过使用至少一个标志信号来使高速同步存储器子系统中的多个存储器件的读取等待时间被均衡。 标志信号具有等效信号传播特性的读时钟信号，从而自动补偿信号传播的影响。 在检测到标志信号之后，存储器件将以预定数量的时钟周期开始输出与先前接收到的读取命令相关联的数据。 对于每个标志信号，存储器控制器在系统初始化时确定在发出读取命令和发出标志信号以均衡系统读取延迟之间所需的延迟。 然后将延迟应用于在存储器系统的常规操作期间读取事务。
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公开(公告)号：US06847583B2
公开(公告)日：2005-01-25
申请号：US10778145
申请日：2004-02-17
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/409 , G11C8/00
CPC分类号： G11C7/1066 , G06F13/1689 , G06F13/4243 , G11C7/1006 , G11C7/1072 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/409 , G11C2207/107 , G11C2207/2254 , G11C2207/2281
摘要： The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.
摘要翻译： 通过使用至少一个标志信号来使高速同步存储器子系统中的多个存储器件的读取等待时间被均衡。 标志信号具有等效信号传播特性的读时钟信号，从而自动补偿信号传播的影响。 在检测到标志信号之后，存储器件将以预定数量的时钟周期开始输出与先前接收到的读取命令相关联的数据。 对于每个标志信号，存储器控制器在系统初始化时确定在发出读取命令和发出标志信号以均衡系统读取延迟之间所需的延迟。 然后将延迟应用于在存储器系统的常规操作期间读取事务。
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公开(公告)号：US06724666B2
公开(公告)日：2004-04-20
申请号：US10222798
申请日：2002-08-19
IPC分类号： G11C700
CPC分类号： G11C7/1066 , G06F13/1689 , G06F13/4243 , G11C7/1006 , G11C7/1072 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/409 , G11C2207/107 , G11C2207/2254 , G11C2207/2281
摘要： The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.
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公开(公告)号：US06851016B2
公开(公告)日：2005-02-01
申请号：US10720183
申请日：2003-11-25
IPC分类号： G06F12/00 , G11C7/10 , G11C7/22 , G11C11/407
CPC分类号： G11C7/22 , G11C7/1072
摘要： In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.
摘要翻译： 在高速存储器子系统中，每个存储器件的最小器件读取延迟和存储器件与存储器控制器之间的信号传播时间差异都会导致系统读取延迟的变化。 本发明通过比较每个设备的系统读取延迟的差异，然后用设备系统读取延迟来操作每个存储器设备来均衡每个存储器设备在高速存储器系统中的系统读取延迟，这使得每个设备呈现相同的系统 读延迟。
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公开(公告)号：US06658523B2
公开(公告)日：2003-12-02
申请号：US09804221
申请日：2001-03-13
IPC分类号： G06F1200
CPC分类号： G11C7/22 , G11C7/1072
摘要： In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.
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公开(公告)号：US09466344B2
公开(公告)日：2016-10-11
申请号：US13489246
申请日：2012-06-05
IPC分类号： G06F12/10 , G11C7/10 , G11C11/4076
CPC分类号： G11C11/4096 , G11C7/1072 , G11C11/40611 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.
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7.发明授权System and method for decoding commands based on command signals and operating state 有权基于命令信号和操作状态对命令进行解码的系统和方法公开(公告)号：US08205055B2
公开(公告)日：2012-06-19
申请号：US12820877
申请日：2010-06-22
IPC分类号： G06F13/16
CPC分类号： G11C11/4096 , G11C7/1072 , G11C11/40611 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.
摘要翻译： 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。
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8.发明授权System and method for decoding commands based on command signals and operating state 有权基于命令信号和操作状态对命令进行解码的系统和方法公开(公告)号：US07757061B2
公开(公告)日：2010-07-13
申请号：US11121868
申请日：2005-05-03
IPC分类号： G06F13/36
CPC分类号： G11C11/4096 , G11C7/1072 , G11C11/40611 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.
摘要翻译： 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。
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公开(公告)号：US06538951B1
公开(公告)日：2003-03-25
申请号：US09941649
申请日：2001-08-30
申请人： Jeffery W. Janzen , Brent Keeth
发明人： Jeffery W. Janzen , Brent Keeth
IPC分类号： G11C800
CPC分类号： G11C11/4093 , G11C7/10
摘要： A method and apparatus for active termination control of a memory module is disclosed. A memory controller provides a single active termination control line per memory module which is used to control memory devices on both sides of a module. The active termination control signal is active for all write functions to the memory devices on the modules. A device read signal generated by the memory devices on one side of the module disables the active termination control signal for memory devices on both sides of the module to enable faster turnarounds between write and read operations.
摘要翻译： 公开了一种用于存储器模块的主动终止控制的方法和装置。 存储器控制器为每个存储器模块提供单个有源终端控制线，其用于控制模块两侧的存储器件。 主动终止控制信号对于模块上的存储器件的所有写入功能都有效。 由模块一侧的存储器件产生的器件读取信号会禁用模块两侧存储器件的有效终止控制信号，从而实现写操作和读操作之间更快的周转。
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10.发明申请SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE 有权基于命令信号和操作状态解码命令的系统和方法公开(公告)号：US20100257332A1
公开(公告)日：2010-10-07
申请号：US12820877
申请日：2010-06-22
CPC分类号： G11C11/4096 , G11C7/1072 , G11C11/40611 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.
摘要翻译： 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。
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