公开(公告)号：US6063711A

公开(公告)日：2000-05-16

申请号：US69456

申请日：1998-04-28

申请人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Chu-Yun Fu ,  Jhon-Jhy Liaw

发明人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Chu-Yun Fu ,  Jhon-Jhy Liaw

IPC分类号： H01L21/768 ,  H01L21/304 ,  B24B1/00 ,  H01L21/461

CPC分类号： H01L21/7681 ,  H01L21/76807

摘要： A high selectivity etch-stop layer comprising oxynitride is disclosed for forming damascene structures in the manufacturing of semiconductor substrates. Because of its relatively high selectivity to oxides, the oxynitride etch-stop can be made thinner than the conventionally used nitride layer. Therefore, the disclosed oxynitride etch-stop layer makes it possible to avoid the cracking problems of thicker etch-stop layers as well as the associated problems of poor definition of contact or via holes in the damascene structure.

摘要翻译： 公开了一种包括氮氧化物的高选择性蚀刻停止层，用于在半导体衬底的制造中形成镶嵌结构。 由于氧化物的选择性相对较高，氧氮化物蚀刻停止可以比常规使用的氮化物层薄。 因此，所公开的氧氮化物蚀刻停止层使得可以避免较厚的蚀刻停止层的破裂问题以及相似的在镶嵌结构中接触或通孔的定义不良的问题。

公开(公告)号：US06214698B1

公开(公告)日：2001-04-10

申请号：US09480270

申请日：2000-01-11

申请人： Jhon-Jhy Liaw ,  Jin-Yuan Lee ,  Kuei-Ying Lee ,  Chu-Yun Fu ,  Kong-Beng Thei

发明人： Jhon-Jhy Liaw ,  Jin-Yuan Lee ,  Kuei-Ying Lee ,  Chu-Yun Fu ,  Kong-Beng Thei

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method for filling a trench within a substrate. First a substrate is provided having a trench formed therein. The trench has a bottom surface and opposing side walls. An undoped silicon glass liner is then thermally grown to coat the bottom surface and side walls of the trench. An undoped silicon oxide layer is then deposited over the undoped silicon glass liner. A boron doped silicon oxide layer is then deposited over the undoped silicon oxide layer, filling the trench. The boron doped silicon oxide layer is then heated to reflow the boron doped silicon oxide to fill any void initially formed within the boron doped silicon oxide layer within the trench, thereby eliminating any void so formed.

摘要翻译： 一种填充衬底内的沟槽的方法。 首先，提供具有形成在其中的沟槽的衬底。 沟槽具有底面和相对的侧壁。 然后将未掺杂的硅玻璃衬里热生长以涂覆沟槽的底表面和侧壁。 然后将未掺杂的氧化硅层沉积在未掺杂的硅玻璃衬垫上。 然后将硼掺杂的氧化硅层沉积在未掺杂的氧化硅层上，填充沟槽。 然后加热硼掺杂的氧化硅层以回流硼掺杂的氧化硅以填充初始形成在沟槽内的硼掺杂的氧化硅层内的任何空隙，从而消除如此形成的任何空隙。

公开(公告)号：US06172411B2

公开(公告)日：2001-01-09

申请号：US09208921

申请日：1998-12-10

申请人： Li-chih Chao ,  Jhon-Jhy Liaw ,  Yuan-Chang Huang ,  Jin-Yuan Lee

发明人： Li-chih Chao ,  Jhon-Jhy Liaw ,  Yuan-Chang Huang ,  Jin-Yuan Lee

IPC分类号： H01L27088

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  Y10S257/90

摘要： A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and silicon oxy-nitride spacers on the sidewalls of the electrode and the cap. An etch stop layer of silicon nitride is deposited over the substrate covering the spacers and cap. A layer of silicon oxide is deposited over the etch stop layer. Etching methods and etchants are used which provide a ratio of the etching rate of silicon oxide to the etching rate of silicon nitride or silicon oxy-nitride of at least eight and a ratio of the etching rate of silicon nitride to the etching rate of silicon oxy-nitride of at least two.

摘要翻译： 描述了自对准结构和蚀刻自对准结构中的接触孔的方法。 选择介电材料，蚀刻方法和蚀刻剂以提供高选择性蚀刻。 该结构包括在电极和盖的侧壁上具有氮氧化硅帽和氮氧化硅间隔物的电极。 氮化硅的蚀刻停止层沉积在覆盖间隔物和盖的衬底上。 氧化硅层沉积在蚀刻停止层上。 使用蚀刻方法和蚀刻剂，其提供氧化硅的蚀刻速率与氮化硅或氮氧化硅的蚀刻速率的比率至少为8，氮化硅的蚀刻速率与硅氧化物的蚀刻速率的比率 至少两个。

公开(公告)号：US5872063A

公开(公告)日：1999-02-16

申请号：US5568

申请日：1998-01-12

申请人： Li-chih Chao ,  Jhon-Jhy Liaw ,  Yuan-Chang Huang ,  Jin-Yuan Lee

发明人： Li-chih Chao ,  Jhon-Jhy Liaw ,  Yuan-Chang Huang ,  Jin-Yuan Lee

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/70

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  Y10S257/90

摘要： A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and silicon oxy-nitride spacers on the sidewalls of the electrode and the cap. An etch stop layer of silicon nitride is deposited over the substrate covering the spacers and cap. A layer of silicon oxide is deposited over the etch stop layer. Etching methods and etchants are used which provide a ratio of the etching rate of silicon oxide to the etching rate of silicon nitride or silicon oxy-nitride of at least eight and a ratio of the etching rate of silicon nitride to the etching rate of silicon oxy-nitride of at least two.

摘要翻译： 描述了自对准结构和蚀刻自对准结构中的接触孔的方法。 选择介电材料，蚀刻方法和蚀刻剂以提供高选择性蚀刻。 该结构包括在电极和盖的侧壁上具有氮氧化硅帽和氮氧化硅间隔物的电极。 氮化硅的蚀刻停止层沉积在覆盖间隔物和盖的衬底上。 氧化硅层沉积在蚀刻停止层上。 使用蚀刻方法和蚀刻剂，其提供氧化硅的蚀刻速率与氮化硅或氮氧化硅的蚀刻速率的比率至少为8，氮化硅的蚀刻速率与硅氧化物的蚀刻速率的比率 至少两个。

公开(公告)号：US09368388B2

公开(公告)日：2016-06-14

申请号：US13446199

申请日：2012-04-13

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L27/11 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

CPC分类号： H01L27/0924 ,  H01L21/76232 ,  H01L21/823431 ,  H01L27/1104 ,  H01L29/66818 ,  H01L29/7853

摘要： A FinFET comprises an isolation region formed in a substrate, a reverse T-shaped fin formed in the substrate, wherein a bottom portion of the reverse T-shaped fin is enclosed by the isolation region and an upper portion of the reverse T-shaped fin protrudes above a top surface of the isolation region. The FinFET further comprises a gate electrode wrapping the reverse T-shaped fin.

公开(公告)号：US08750011B2

公开(公告)日：2014-06-10

申请号：US13423968

申请日：2012-03-19

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： G11C5/06

CPC分类号： G11C17/12 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11226 ,  H01L27/1211

摘要： A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a first second-level contact formed on the first first-level contact, wherein the first second-level contact shifts in a first direction with reference to the first first-level contact. The ROM cell further comprises a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is aligned with the first first-level contact and a second second-level formed on the second first-level contact, wherein the second second-level contact shifts in a second direction with reference to the second first-level contact, and wherein the first direction is opposite to the second direction.

摘要翻译： ROM单元包括形成在存储单元的晶体管的第一有源区上的第一第一电平触点，形成在第一第一级触点上的第一二级触点，其中第一二级触点以第一 方向参考第一级联系人。 ROM单元还包括形成在存储器单元的晶体管的第二有源区上的第二第一电平触点，其中第二第一电平触点与第一第一电平触点对准，第二二级触点形成在第二电平触点上 第二第一级触点，其中所述第二二级触头相对于所述第二第一级触点沿第二方向移动，并且其中所述第一方向与所述第二方向相反。

公开(公告)号：US08625334B2

公开(公告)日：2014-01-07

申请号：US13328685

申请日：2011-12-16

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H01L27/1104

摘要： A memory cell and array and a method of forming a memory cell and array are described. A memory cell includes first and second pull-up transistors, first and second pull-down transistors, first and second pass-gate transistors, and first and second isolation transistors. Drains of the first pull-up and first pull-down transistors are electrically coupled together at a first node. Drains of the second pull-up and second pull-down transistors are electrically coupled together at a second node. Gates of the second pull-up and second pull-down transistors are electrically coupled to the first node, and gates of the first pull-up and first pull-down transistors are electrically coupled to the second node. The first and second pass-gate transistors are electrically coupled to the first and second nodes, respectively. The first and second isolation transistors are electrically coupled to the first and second nodes, respectively.

公开(公告)号：US20130270652A1

公开(公告)日：2013-10-17

申请号：US13446199

申请日：2012-04-13

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/088

CPC分类号： H01L27/0924 ,  H01L21/76232 ,  H01L21/823431 ,  H01L27/1104 ,  H01L29/66818 ,  H01L29/7853

摘要： A FinFET comprises an isolation region formed in a substrate, a reverse T-shaped fin formed in the substrate, wherein a bottom portion of the reverse T-shaped fin is enclosed by the isolation region and an upper portion of the reverse T-shaped fin protrudes above a top surface of the isolation region. The FinFET further comprises a gate electrode wrapping the reverse T-shaped fin.

摘要翻译： FinFET包括形成在衬底中的隔离区域，形成在衬底中的反向T形翅片，其中反向T形翅片的底部被隔离区域包围，并且反向T形翅片的上部 突出在隔离区域的顶表面上方。 FinFET还包括一个包围反向T形翅片的栅电极。

公开(公告)号：US08409964B2

公开(公告)日：2013-04-02

申请号：US13399488

申请日：2012-02-17

申请人： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

发明人： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

IPC分类号： H01L21/76

CPC分类号： H01L21/823878 ,  H01L21/76232

摘要： A shallow trench isolation (STI) structure and methods of forming a STI structure are disclosed. An embodiment is a method for forming a semiconductor structure. The method includes forming a recess in a semiconductor substrate; forming a first material on sidewalls of the recess; forming a widened recessed portion through a bottom surface of the recess; removing the first material from the sidewalls of the recess; and forming a dielectric material in the recess and the widened recessed portion. The bottom surface of the recess is exposed through the first material, and the bottom surface of the recess has a first width. The widened recessed portion has a second width. The second width is greater than the first width.

摘要翻译： 公开了浅沟槽隔离（STI）结构和形成STI结构的方法。 实施例是形成半导体结构的方法。 该方法包括在半导体衬底中形成凹陷; 在所述凹部的侧壁上形成第一材料; 通过所述凹部的底面形成加宽的凹部; 从所述凹部的侧壁去除所述第一材料; 以及在所述凹部和所述加宽的凹部中形成介电材料。 凹部的底面通过第一材料露出，凹部的底面具有第一宽度。 加宽的凹部具有第二宽度。 第二宽度大于第一宽度。

公开(公告)号：US20120319212A1

公开(公告)日：2012-12-20

申请号：US13598093

申请日：2012-08-29

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/088

CPC分类号： H01L27/11 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/41791 ,  H01L29/785

摘要： A static random access memory (SRAM) cell includes a straight fin and a bended fin physically disconnected from the straight fin. The bended fin has a first portion and a second portion parallel to the straight fin. The distance between the first portion of the bended fin and the straight fin is smaller than the distance between the second portion of the bended fin and the straight fin. The SRAM cell includes a pull-down transistor including a portion of a first gate strip, which forms a first and a second sub pull-down transistor with the straight fin and the first portion of the bended fin, respectively. The SRAM cell further includes a pass-gate transistor including a portion of a second gate strip, which forms a first sub pass-gate transistor with the straight fin. The pull-down transistor includes more fins than the pass-gate transistor.

摘要翻译： 静态随机存取存储器（SRAM）单元包括与直翅片物理断开的直翅片和弯曲的翅片。 弯曲的翅片具有平行于直翅片的第一部分和第二部分。 弯曲翅片的第一部分和直翅片之间的距离小于弯曲翅片的第二部分和直翅片之间的距离。 SRAM单元包括下拉晶体管，其包括第一栅极条的一部分，其分别与直鳍和弯曲鳍的第一部分形成第一和第二子下拉晶体管。 SRAM单元还包括一个包括第二栅极条的一部分的通过栅极晶体管，其形成具有直的鳍的第一子栅极晶体管。 下拉晶体管包括比传输栅极晶体管更多的鳍片。