公开(公告)号：US6063711A

公开(公告)日：2000-05-16

申请号：US69456

申请日：1998-04-28

申请人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Chu-Yun Fu ,  Jhon-Jhy Liaw

发明人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Chu-Yun Fu ,  Jhon-Jhy Liaw

IPC分类号： H01L21/768 ,  H01L21/304 ,  B24B1/00 ,  H01L21/461

CPC分类号： H01L21/7681 ,  H01L21/76807

摘要： A high selectivity etch-stop layer comprising oxynitride is disclosed for forming damascene structures in the manufacturing of semiconductor substrates. Because of its relatively high selectivity to oxides, the oxynitride etch-stop can be made thinner than the conventionally used nitride layer. Therefore, the disclosed oxynitride etch-stop layer makes it possible to avoid the cracking problems of thicker etch-stop layers as well as the associated problems of poor definition of contact or via holes in the damascene structure.

摘要翻译： 公开了一种包括氮氧化物的高选择性蚀刻停止层，用于在半导体衬底的制造中形成镶嵌结构。 由于氧化物的选择性相对较高，氧氮化物蚀刻停止可以比常规使用的氮化物层薄。 因此，所公开的氧氮化物蚀刻停止层使得可以避免较厚的蚀刻停止层的破裂问题以及相似的在镶嵌结构中接触或通孔的定义不良的问题。

公开(公告)号：US06323121B1

公开(公告)日：2001-11-27

申请号：US09570018

申请日：2000-05-12

申请人： Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui

发明人： Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui

IPC分类号： H01L214763

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76807

摘要： A method is described for cleaning freshly etched dual damascene via openings and preparing them for copper fill without damage or contamination of exposed organic or other porous low-k insulative layers. The method is entirely dry and does not expose the porous materials to contamination from moisture or solvents. The method is effective for removing all traces of residual polymer deposits from an in-process substrate wafers after via or damascene trench etching. The method employs an in-situ three-step treatment comprising a first step of exposing the electrically biased substrate wafer to a O2/N2 ashing plasma to remove photoresist and polymers, a second step immediately following the first step of remove silicon nitride etch stop layers, and a final step of treating the wafer with H2/N2 to remove copper polymer deposits formed during nitride removal. The H2/N2 plasma is capable of removing the difficult polymer residues which are otherwise only removable by wet stripping procedures. The H2/N2 plasma is not harmful to exposed porous low-k dielectric layers as well as copper metallurgy.

摘要翻译： 描述了一种用于通过开口清洁新鲜蚀刻的双镶嵌件的方法，并且它们用于铜填充而不损坏或污染暴露的有机或其它多孔低k绝缘层。 该方法是完全干燥的，并且不会使多孔材料暴露于水分或溶剂的污染物中。 该方法对于在通孔或镶嵌沟槽蚀刻之后从工艺衬底晶片去除残余聚合物沉积物的所有迹线是有效的。 该方法采用原位三步处理，其包括将电偏置的衬底晶片暴露于O 2 / N 2灰分等离子体以去除光致抗蚀剂和聚合物的第一步骤，紧接着在去除氮化硅蚀刻停止层的第一步骤之后的第二步骤 ，以及用H2 / N2处理晶片以除去在氮化物除去期间形成的铜聚合物沉积物的最后步骤。 H 2 / N 2等离子体能够去除困难的聚合物残余物，否则其仅可通过湿式剥离方法除去。 H2 / N2等离子体对暴露的多孔低k电介质层以及铜冶金无害。

公开(公告)号：US06743732B1

公开(公告)日：2004-06-01

申请号：US09769812

申请日：2001-01-26

申请人： Li-Te Lin ,  Li-Chih Chao ,  Chia-Shiung Tsai

发明人： Li-Te Lin ,  Li-Chih Chao ,  Chia-Shiung Tsai

IPC分类号： H01L21302

CPC分类号： H01L21/76811 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76802 ,  H01L21/76813

摘要： A plasma etch process for organic low-k dielectric layers using NH3 only, or NH3/H2 or NH3/H2 gases. A low k dielectric layer is formed over a substrate. A masking pattern is formed over the low k dielectric layer. The masking pattern has an opening. Using the invention's etch process, the low k dielectric layer is etched through the opening using the masking pattern as an etch mask. In a first embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3 gas. In a second embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/H2 gas. In a third embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/N2 gas. The invention's NH3 containing plasma etch etches organic Low k materials unexpectedly fast. The invention's NH3 only etch had a 30 to 80% high etch rate than N2/H2 etches of low-k materials like Silk™.

摘要翻译： 仅使用NH3或NH3 / H2或NH3 / H2气体的有机低k电介质层的等离子体蚀刻工艺。 在衬底上形成低k电介质层。 在低k电介质层上形成掩模图案。 掩模图案具有开口。 使用本发明的蚀刻工艺，使用掩模图案作为蚀刻掩模，通过开口蚀刻低k电介质层。 在第一实施例中，蚀刻工艺包括：通过施加等离子体功率并仅流过NH 3气体来蚀刻低k电介质层。 在第二实施例中，蚀刻工艺包括：通过施加等离子体功率并仅流过NH 3 / H 2气体来蚀刻低k电介质层。 在第三实施例中，蚀刻工艺包括：通过施加等离子体功率并仅流过NH 3 / N 2气体来蚀刻低k电介质层。 本发明的含NH 3的等离子体蚀刻意外地快速蚀刻有机低k材料。 本发明的仅NH3蚀刻具有比Silk TM的低k材料的N 2 / H 2蚀刻高30至80％的高蚀刻速率。

公开(公告)号：US06429119B1

公开(公告)日：2002-08-06

申请号：US09405059

申请日：1999-09-27

申请人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Chao-Cheng Chen

发明人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Chao-Cheng Chen

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/76813 ,  H01L2221/1063

摘要： Using this special dual damascene process, interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of thin etch stop or etch barrier layers. The key process steps of this invention are a special partial via hole etch and a special via hole liner. The Prior Art dual damascene processes are generally composed of a thick via etch stop layer to avoid damaging underlying Cu during via patterning, as well as, a thick trench etch stop layer to avoid via hole facet during trench patterning. Thick etch stop layers are undesirably due to high dielectric constant values compared with silicon oxide, the intermetal dielectric (IMD). Therefore, the thickness of stop-layer should be reduced to minimize the circuit (RC) time constant delay. In general, there are two main approaches for dual damascene etching. One of the main approaches use self-aligned dual damascene (SADD) etching which requires a thick trench etching stop-layer thickness. The other approach use counter-bore method which requires a thick via etching stop-layer thickness. This invention describes a novel dual damascene process which can minimize the thickness of both via and trench etching stop-layer, while avoiding deleterious damage to the underlying to and via facet profile during via and trench etching.

摘要翻译： 使用这种特殊的双镶嵌工艺，形成具有低寄生电容（低RC时间常数）的互连导线和通孔触点。 本发明包括使用薄蚀刻停止层或蚀刻阻挡层。 本发明的关键工艺步骤是特殊的部分通孔蚀刻和特殊通孔衬垫。 现有技术的双镶嵌工艺通常由厚的通孔蚀刻停止层组成，以避免在通孔图案化期间损坏下面的铜，以及在沟槽图案化期间避免通孔小面的厚沟槽蚀刻停止层。 与氧化硅（金属间电介质（IMD））相比，由于高的介电常数值，厚的蚀刻停止层是不期望的。 因此，应该减小停止层的厚度以最小化电路（RC）时间常数延迟。 一般来说，双镶嵌蚀刻有两种主要方法。 主要方法之一使用自对准双镶嵌（SADD）蚀刻，其需要厚沟槽蚀刻停止层厚度。 另一种方法使用需要厚通孔蚀刻停止层厚度的反孔法。 本发明描述了一种新颖的双镶嵌工艺，其可以最小化通孔和沟槽蚀刻停止层的厚度，同时避免在通孔和沟槽蚀刻期间对于底面和经过小面轮廓的有害损伤。

公开(公告)号：US06458650B1

公开(公告)日：2002-10-01

申请号：US09908821

申请日：2001-07-20

申请人： Yi-Chen Huang ,  Li-Chih Chao ,  Chao-Chen Chen

发明人： Yi-Chen Huang ,  Li-Chih Chao ,  Chao-Chen Chen

IPC分类号： H01L218242

CPC分类号： H01L28/91 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31629 ,  H01L21/3185 ,  H01L21/76802 ,  H01L21/76814

摘要： A new method is provided for the creation of an opening over which the second electrode of a MIM capacitor is to be deposited. The first electrode of the MIM is created in a first layer of Fluorine doped Silicon dioxide (SiO2) Glass (FSG) . A layer of insulation comprising silicon nitride is deposited over the surface of the first electrode. A second layer of Fluorine doped Silicon dioxide (SiO2) Glass (FSG) is deposited over the surface of the layer of silicon nitride, an etch stop layer of silicon nitride is deposited over the surface of the second layer of FSG. The layers of etch stop and the second layer of FSG are patterned and etched using a dry etch, stopping on the layer-of insulation and exposing the surface of the layer of insulation. Next-and of critical importance to the invention is a step of photoresist ashing and oxidation of the surface of the layer of silicon nitride. The layer of photoresist can now be removed while concurrently, using a wet strip, the layer of silicon nitride oxidation is removed from the surface of the layer of silicon nitride. The process of creating a MIM capacitor can then proceed by creating the second electrode of the MIM capacitor.

摘要翻译： 提供了一种新的方法，用于创建MIM电容器的第二电极将要沉积的开口。 MIM的第一电极在氟掺杂二氧化硅（SiO 2）玻璃（FSG）的第一层中产生。 包含氮化硅的绝缘层沉积在第一电极的表面上。 氟化二氧化硅（SiO 2）玻璃（FSG）的第二层沉积在氮化硅层的表面上，氮化硅的蚀刻停止层沉积在第二层FSG的表面上。 蚀刻停止层和FSG的第二层被图案化和蚀刻使用干蚀刻，停止在绝缘层上并暴露绝缘层的表面。 接下来对于本发明至关重要的是对氮化硅层的表面的光致抗蚀剂灰化和氧化的步骤。 现在可以同时去除光致抗蚀剂层，使用湿条，从氮化硅层的表面去除氮化硅层的氧化层。 然后可以通过产生MIM电容器的第二电极来进行制造MIM电容器的过程。

公开(公告)号：US06727183B1

公开(公告)日：2004-04-27

申请号：US09915842

申请日：2001-07-27

申请人： Ching-Hui Ma ,  Jen-Cheng Liu ,  Li-Chih Chao

发明人： Ching-Hui Ma ,  Jen-Cheng Liu ,  Li-Chih Chao

IPC分类号： H01L21302

CPC分类号： H01L21/76814 ,  H01L21/31116 ,  H01L21/76807

摘要： A novel etching method for preventing spiking and undercutting of an ultra low-k material layer in damascene metallization is described. A region to be contacted is provided in or on a semiconductor substrate. A liner layer is deposited overlying the region to be contacted. An ultra low-k dielectric layer is deposited overlying the liner layer. A damascene opening is etched through the ultra low-k dielectric layer to the liner layer overlying the region to be contacted wherein this etching comprises a high F/C ratio etch chemistry, high power, and low pressure. The liner layer within the damascene opening is etched away to expose the region to be contacted wherein this etching comprises a high F/C ratio etch chemistry, low power, and low pressure to complete formation of a damascene opening in the fabrication of an integrated circuit device.

摘要翻译： 描述了一种用于防止镶嵌金属化中的超低k材料层的尖锐和底切的新颖蚀刻方法。 待接触的区域设置在半导体衬底中或其上。 衬垫层被覆盖在待接触的区域上。 沉积在衬层上的超低k电介质层。 通过超低k电介质层将镶嵌开口蚀刻到覆盖待接触区域的衬垫层，其中该蚀刻包括高F / C比蚀刻化学，高功率和低压。 镶嵌开口内的衬里层被蚀刻掉以暴露待接触的区域，其中该蚀刻包括高F / C比蚀刻化学，低功率和低压，以在集成电路的制造中完成镶嵌开口的形成 设备。

公开(公告)号：US6165880A

公开(公告)日：2000-12-26

申请号：US94869

申请日：1998-06-15

申请人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Li-Chih Chao ,  Kuo Ching Huang

发明人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Li-Chih Chao ,  Kuo Ching Huang

IPC分类号： H01L21/285 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L21/32053

摘要： A method was achieved for making improved self-aligned contacts (SAC) to a patterned polysilicon layer, such as gate electrodes for FETs. Lightly doped source/drain areas are implanted. A second insulating layer is deposited and etched back to form first sidewall spacers. A silicon nitride etch-stop layer and a first interpolysilicon oxide (IPO1) layer are deposited. First SAC openings are etched in the IPO1 layer to the etch-stop layer, and concurrently openings are etched for the gate electrodes, eliminating a masking step. The etch-stop layer is etched in the SAC openings to form second sidewall spacers that protect the first sidewall spacers during BOE cleaning of the contacts. A patterned polycide layer is used to make SACs and electrical interconnections. A second IPO layer is deposited to provide insulation, and an interlevel dielectric layer is deposited. Second SAC openings are etched to the etch-stop layer for the next level of metal interconnections, while the contact openings to the gate electrodes are etched to completion. The etch-stop layer is etched in the second SAC openings to form second sidewall spacers to protect the first sidewall spacers during cleaning. Metal plugs are formed from a first metal in the second SAC openings and in the openings to the gate electrodes. A second metal is patterned to complete the structure to the first level of metal interconnections.

摘要翻译： 实现了对图案化多晶硅层（例如FET的栅电极）进行改进的自对准接触（SAC）的方法。 植入轻掺杂的源极/漏极区域。 沉积第二绝缘层并回蚀刻以形成第一侧壁间隔物。 沉积氮化硅蚀刻停止层和第一多晶硅化硅（IPO1）层。 在IPO1层中蚀刻第一SAC开口到蚀刻停止层，同时蚀刻用于栅电极的开口，从而消除掩模步骤。 在SAC开口中蚀刻蚀刻停止层以形成第二侧壁间隔物，其在接触的BOE清洁期间保护第一侧壁间隔物。 使用图案化的多晶硅化合物层来制造SAC和电互连。 沉积第二个IPO层以提供绝缘，并且沉积层间电介质层。 将第二SAC开口蚀刻到蚀刻停止层以进行下一级金属互连，同时蚀刻到栅电极的接触开口以完成。 在第二SAC开口中蚀刻蚀刻停止层以形成第二侧壁间隔物，以在清洁期间保护第一侧壁间隔物。 金属插塞由第二SAC开口中的第一金属和与栅电极的开口形成。 图案化第二金属以将结构完成到第一级金属互连。

公开(公告)号：US6140218A

公开(公告)日：2000-10-31

申请号：US329782

申请日：1999-06-10

申请人： Jen-Cheng Liu ,  Li-Chih Chao ,  Huan-Just Lin ,  Yung-Kuan Hsiao

发明人： Jen-Cheng Liu ,  Li-Chih Chao ,  Huan-Just Lin ,  Yung-Kuan Hsiao

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/60 ,  H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/0334 ,  H01L21/28123

摘要： The present invention provides a method of fabricating a T-shaped hard mask/conductive pattern profile and a process of etching a self-aligned contact opening using a T-shaped hard mask/conductive pattern profile to improve the self-aligned contact isolation. The process begins by forming a polysilicon or more preferably a polysilicon/silicide conductive layer over a semiconductor substrate. A silicon oxynitride hard mask layer is formed over the conductive layer. The silicon oxynitride hard mask layer is patterned to form a hard mask pattern. The conductive layer is patterned to form a conductive pattern in a three step etch using Cl.sub.2 and HBr chemistry. The silicon oxynitride hard mask releases oxygen during the conductive layer etch resulting in a T-shaped hard mask/conductive pattern profile (e.g. the width of the hard mask is greater than the width of the conductive pattern after etching). In a preferred embodiment, the a T-shaped hard mask/conductive pattern profile is used to form a self-aligned contact for a capacitor over bitline structure.

摘要翻译： 本发明提供了一种制造T形硬掩模/导电图案轮廓的方法以及使用T形硬掩模/导电图案轮廓蚀刻自对准接触开口的过程，以改善自对准接触隔离。 该过程通过在半导体衬底上形成多晶硅或更优选多晶硅/硅化物导电层开始。 在导电层上形成氧氮化硅硬掩模层。 将氮氧化硅硬掩模层图案化以形成硬掩模图案。 使用Cl2和HBr化学，在三步蚀刻中对导电层进行图案化以形成导电图案。 氧氮化硅硬掩模在导电层蚀刻期间释放氧，导致T形硬掩模/导电图案轮廓（例如，硬掩模的宽度大于蚀刻后的导电图案的宽度）。 在优选实施例中，T形硬掩模/导电图形轮廓用于通过位线结构形成用于电容器的自对准接触。

公开(公告)号：US20050014362A1

公开(公告)日：2005-01-20

申请号：US10915633

申请日：2004-08-10

申请人： Bang-Chien Ho ,  Jian-Hong Chen ,  Tsang-Jiuh Wu ,  Li-Te Lin ,  Li-Chih Chao ,  Hua-Tai Lin ,  Shyue-Sheng Lu

发明人： Bang-Chien Ho ,  Jian-Hong Chen ,  Tsang-Jiuh Wu ,  Li-Te Lin ,  Li-Chih Chao ,  Hua-Tai Lin ,  Shyue-Sheng Lu

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76808

摘要： A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.

摘要翻译： 使用双镶嵌工艺制造半导体器件的方法来在由各种高蚀刻材料和底部抗反射涂层（BARC）材料构成的通孔中形成插塞。 在通孔蚀刻之后，旋涂一层高蚀刻速率的塞材料以填充通孔。 接下来，施加一层光致抗蚀剂。 然后将光致抗蚀剂通过掩模曝光并显影以形成蚀刻开口。 使用剩余的光致抗蚀剂作为蚀刻掩模和底部防反射涂层（BARC）作为保护，氧化物或低k层被蚀刻以形成后续布线。 蚀刻步骤被称为镶嵌蚀刻步骤。 去除剩余的光致抗蚀剂，并且通过金属形成金属互连布线和接触通孔填充沟槽/通孔开口。

公开(公告)号：US06495469B1

公开(公告)日：2002-12-17

申请号：US09999309

申请日：2001-12-03

申请人： Jiing-Feng Yang ,  Li-Te S. Lin ,  Li-Chih Chao

发明人： Jiing-Feng Yang ,  Li-Te S. Lin ,  Li-Chih Chao

IPC分类号： H01L21302

CPC分类号： H01L21/76807 ,  H01L21/0276 ,  H01L21/31116

摘要： A method for etching a dielectric layer comprising the following steps. A structure having a low-k dielectric layer formed thereover is provided. A DARC layer is formed over the low-k dielectric layer. A patterned masking layer is formed over the DARC layer. Using the patterned masking layer as a mask, the DARC layer and the low-k dielectric layer are etched employing an CHxFy/O2/N2/Ar etch chemistry.

摘要翻译： 一种用于蚀刻介电层的方法，包括以下步骤。 提供了一种其上形成有低k电介质层的结构。 在低k电介质层上形成DARC层。 在DARC层上形成图案化掩模层。 使用图案化掩模层作为掩模，使用CHxFy / O 2 / N 2 / Ar蚀刻化学法蚀刻DARC层和低k电介质层。