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45 条记录 (耗时 0.046 秒)

    Synchronizing data between devices
    1.
    发明授权
    Synchronizing data between devices 失效
    在设备之间同步数据

    公开(公告)号：US5822571A

    公开(公告)日：1998-10-13

    申请号：US659142

    申请日：1996-06-05

    申请人： Alan L. Goodrum ,  Jens K. Ramsey ,  Paul R. Culley ,  Joseph P. Miller

    发明人： Alan L. Goodrum ,  Jens K. Ramsey ,  Paul R. Culley ,  Joseph P. Miller

    IPC分类号： G06F13/36 ,  G06F1/12 ,  G06F13/40 ,  G06F13/42 ,  G06F5/06

    CPC分类号： G06F13/405

    摘要： Data is transmitted between a first device and a second device connected by the communications channel in a computer system. The first device generates a first clock and the second device generates a second clock. The first clock is provided to the second device and the second clock is provided to the first device. Data received by the first device over the communications channel from the second device is synchronized to the first clock. The receiving logic in the first device includes a first-in-first-out buffer The received data is stored in a first-in-first-out buffer until the data is synchronized to the first clock. The first and second clocks have the same frequency.

    摘要翻译： 在计算机系统中，通过通信信道连接的第一设备和第二设备之间传送数据。 第一设备产生第一时钟，第二设备产生第二时钟。 将第一时钟提供给第二设备，并且将第二时钟提供给第一设备。 由第一设备通过通信信道从第二设备接收的数据被同步到第一时钟。 第一设备中的接收逻辑包括先进先出缓冲器。接收到的数据被存储在先进先出缓冲器中，直到数据与第一时钟同步。 第一和第二个时钟具有相同的频率。

    Bus arbitration
    2.
    发明授权
    Bus arbitration 失效
    总线仲裁

    公开(公告)号：US5872939A

    公开(公告)日：1999-02-16

    申请号：US658485

    申请日：1996-06-05

    申请人： Jens K. Ramsey ,  Alan L. Goodrum ,  Paul R. Culley

    发明人： Jens K. Ramsey ,  Alan L. Goodrum ,  Paul R. Culley

    IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/00

    CPC分类号： G06F13/364

    摘要： Access to a bus in a computer system having a CPU and bus devices capable of running cycles on a bus is controlled by an arbiter. The arbiter grants access to the bus according to an arbitration scheme that depends on whether a request for the bus is pending from the CPU, in which a first arbitration scheme arbitrates between the bus devices, and wherein a second arbitration scheme arbitrates between the CPU and at least one other bus device if the CPU request is present.

    摘要翻译： 具有能够在总线上运行循环的CPU和总线设备的计算机系统中的总线的访问由仲裁器控制。 仲裁器根据仲裁方案授予对总线的访问，该仲裁方案取决于来自CPU的总线请求是否等待，其中第一仲裁方案在总线设备之间进行仲裁，并且其中第二仲裁方案在CPU和 如果存在CPU请求，则至少另外一个总线设备。

    Storing data associated with one request while continuing to store data associated with a previous request from the same device
    8.
    发明授权
    Storing data associated with one request while continuing to store data associated with a previous request from the same device 失效
    存储与一个请求相关联的数据，同时继续存储与来自同一设备的先前请求相关联的数据

    公开(公告)号：US6035362A

    公开(公告)日：2000-03-07

    申请号：US658728

    申请日：1996-06-05

    申请人： Alan L. Goodrum ,  John M. MacLaren ,  Paul R. Culley

    发明人： Alan L. Goodrum ,  John M. MacLaren ,  Paul R. Culley

    IPC分类号： G06F13/36 ,  G06F12/08 ,  G06F13/40

    CPC分类号： G06F13/4059

    摘要： A computer system includes a first device on the first data bus, a second device on the second data bus, and a bridge device that delivers requests for data from the first device to the second device and returns the requested data to the first device. The bridge device includes a first data storage buffer that stores data requested by the first device during the first request, and a second data buffer that simultaneously stores data requested by the first device during a second request.

    摘要翻译： 计算机系统包括第一数据总线上的第一设备，第二数据总线上的第二设备以及将数据从第一设备传送到第二设备并将所请求的数据返回到第一设备的桥接设备。 桥接器件包括第一数据存储缓冲器，其存储在第一请求期间由第一器件请求的数据，以及第二数据缓冲器，其在第二请求期间同时存储由第一器件请求的数据。

    Computer system bus performance monitoring
    9.
    发明授权
    Computer system bus performance monitoring 失效
    计算机系统总线性能监控

    公开(公告)号：US5819053A

    公开(公告)日：1998-10-06

    申请号：US658696

    申请日：1996-06-05

    申请人： Alan L. Goodrum ,  Paul R. Culley

    发明人： Alan L. Goodrum ,  Paul R. Culley

    IPC分类号： G06F13/36 ,  G06F11/34 ,  G06F13/362 ,  H01J13/00

    CPC分类号： G06F11/349 ,  G06F11/3495

    摘要： Performance of a bus in a computer system is monitored. A predetermined total period is counted, and usage of the bus for data transfers during the total period is measured. The bus is monitored for active cycles and a period is counted in which the active cycles are present during the total period. The bus is monitored for data transfer cycles and a period is counted in which the data transfer cycles are present during the total period. Bus efficiency is measured based on the active period and data transfer period. Read data usage on the bus is also measured. A first amount of data read by a first device is monitored, and a second amount of read data used by a second bus device is monitored. The read efficiency is determined based on the first and second amounts.

    摘要翻译： 监控计算机系统中总线的性能。 对预定的总时段进行计数，并且测量在总时段期间用于数据传输的总线的使用。 监控总线的有效周期，并计算在整个周期内存在有效周期的周期。 监视总线进行数据传输周期，并计算在整个周期内存在数据传输周期的周期。 总线效率是根据活动期和数据传输周期来测量的。 也读取总线上的数据使用情况。 监视由第一设备读取的第一数据量，并且监视由第二总线设备使用的第二数量的读取数据。 基于第一和第二量确定读取效率。

    Dynamic Converter Control for Efficient Operation
    10.
    发明申请
    Dynamic Converter Control for Efficient Operation 有权
    动态转换器控制高效运行

    公开(公告)号：US20080320322A1

    公开(公告)日：2008-12-25

    申请号：US11768102

    申请日：2007-06-25

    申请人： Alan M. Green ,  Alan L. Goodrum

    发明人： Alan M. Green ,  Alan L. Goodrum

    IPC分类号： G06F11/30 ,  G06F1/26

    CPC分类号： G06F1/26 ,  G06F1/263 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/172 ,  Y10T307/549

    摘要： Dynamically managing power consumption in a computer system having at least two parallel power converters in order to improve efficiency. A maximum power capacity for each of the power converters is determined and then power consumption of the computer system is monitored. If the power consumption of the computer system can be provided by less than all of the parallel power converters then one or more of the power converters is turned off, such that a reduced number of parallel power converters remains turned on. A reduced maximum power capacity of the reduced number of parallel power converters is determined and a power cap value is set for the computer system that is less than or equal to the reduced maximum power capacity. The computer system is throttled at the power cap to prevent power consumption of the computer system from exceeding the power cap value.

    摘要翻译： 动态地管理具有至少两个并联电力转换器的计算机系统中的功率消耗，以便提高效率。 确定每个功率转换器的最大功率容量，然后监视计算机系统的功耗。 如果计算机系统的功率消耗可以由小于所有并行功率转换器提供，则一个或多个功率转换器被关闭，使得并联功率转换器的数量减少。 确定并联功率转换器数量减少的最大功率容量降低，并且为计算机系统设置功率上限值小于或等于降低的最大功率容量。 计算机系统在电源盖上节流，以防止计算机系统的功耗超过功率上限值。