摘要:
An electrode structure, a GaN-based semiconductor device including the electrode structure, and methods of manufacturing the same, may include a GaN-based semiconductor layer and an electrode structure on the GaN-based semiconductor layer. The electrode structure may include an electrode element including a conductive material and a diffusion layer between the electrode element and the GaN-based semiconductor layer. The diffusion layer may include a material which is an n-type dopant with respect to the GaN-based semiconductor layer, and the diffusion layer may contact the GaN-based semiconductor layer. A region of the GaN-based semiconductor layer contacting the diffusion layer may be doped with the n-type dopant. The material of the diffusion layer may comprise a Group 4 element.
摘要:
An electrode structure, a GaN-based semiconductor device including the electrode structure, and methods of manufacturing the same, may include a GaN-based semiconductor layer and an electrode structure on the GaN-based semiconductor layer. The electrode structure may include an electrode element including a conductive material and a diffusion layer between the electrode element and the GaN-based semiconductor layer. The diffusion layer may include a material which is an n-type dopant with respect to the GaN-based semiconductor layer, and the diffusion layer may contact the GaN-based semiconductor layer. A region of the GaN-based semiconductor layer contacting the diffusion layer may be doped with the n-type dopant. The material of the diffusion layer may comprise a Group 4 element.
摘要:
Example methods may provide a thin film etching method. Example thin film etching methods may include forming a Ga—In—Zn—O film on a substrate, forming a mask layer covering a portion of the Ga—In—Zn—O film, and etching the Ga—In—Zn—O film using the mask layer as an etch barrier, wherein an etching gas used in the etching includes chlorine. The etching gas may further include an alkane (CnH2n+2) and H2 gas. The chlorine gas may be, for example, Cl2, BCl3, and/or CCl3, and the alkane gas may be, for example, CH4.
摘要翻译:示例性方法可以提供薄膜蚀刻方法。 示例性薄膜蚀刻方法可以包括在衬底上形成Ga-In-Zn-O膜,形成覆盖Ga-In-Zn-O膜的一部分的掩模层,并且蚀刻Ga-In-Zn-O膜 使用掩模层作为蚀刻阻挡层,其中在蚀刻中使用的蚀刻气体包括氯。 蚀刻气体还可以包括烷烃(C n H 2n + 2)和H 2气体。 氯气可以是例如Cl 2,BCl 3和/或CCl 3,并且烷烃气体可以是例如CH 4。
摘要:
Example methods may provide a thin film etching method. Example thin film etching methods may include forming a Ga—In—Zn—O film on a substrate, forming a mask layer covering a portion of the Ga—In—Zn—O film, and etching the Ga—In—Zn—O film using the mask layer as an etch barrier, wherein an etching gas used in the etching includes chlorine. The etching gas may further include an alkane (CnH2n+2) and H2 gas. The chlorine gas may be, for example, Cl2, BCl3, and/or CCl3, and the alkane gas may be, for example, CH4.
摘要翻译:示例性方法可以提供薄膜蚀刻方法。 示例性薄膜蚀刻方法可以包括在衬底上形成Ga-In-Zn-O膜,形成覆盖Ga-In-Zn-O膜的一部分的掩模层,并且蚀刻Ga-In-Zn-O膜 使用掩模层作为蚀刻阻挡层,其中在蚀刻中使用的蚀刻气体包括氯。 蚀刻气体还可以包括烷烃(C n H 2 H 2n + 2 H 2)和H 2 H 2气体。 氯气可以是例如Cl 2,BCl 3和/或CCl 3,烷烃气体可以是 例如CH 4。
摘要:
Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a substrate and a plurality of semiconductor pillars on the substrate. A plurality of control gate electrodes may be stacked on the substrate and intersecting the plurality of semiconductor pillars. A plurality of dummy electrodes may be stacked adjacent to the plurality of control gate electrodes on the substrate, the plurality of dummy electrodes being spaced apart from the plurality of control gate electrodes. A plurality of via plugs may be connected to the plurality of control gate electrodes. A plurality of wordlines may be on the plurality of via plugs. Each of the plurality of via plugs may penetrate a corresponding one of the plurality of control gate electrodes and at least one of the plurality of dummy electrodes.
摘要:
Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a substrate and a plurality of semiconductor pillars on the substrate. A plurality of control gate electrodes may be stacked on the substrate and intersecting the plurality of semiconductor pillars. A plurality of dummy electrodes may be stacked adjacent to the plurality of control gate electrodes on the substrate, the plurality of dummy electrodes being spaced apart from the plurality of control gate electrodes. A plurality of via plugs may be connected to the plurality of control gate electrodes. A plurality of wordlines may be on the plurality of via plugs. Each of the plurality of via plugs may penetrate a corresponding one of the plurality of control gate electrodes and at least one of the plurality of dummy electrodes.
摘要:
Provided are phase change random access memory (PRAM) devices and methods of operating the same. The PRAM device may include a switching device, a lower electrode, a lower electrode contact layer, a phase change layer and/or an upper electrode. The lower electrode may be connected to a switching device. The lower electrode contact layer may be formed on the lower electrode. The phase change layer, which may include a bottom surface that contacts an upper surface of the lower electrode contact layer, may be formed on the lower electrode contact layer. The upper electrode may be formed on the phase change layer. The lower electrode contact layer may be formed of a material layer having an absolute value of a Seebeck coefficient higher than TiAlN. The Seebeck coefficient of the lower electrode contact layer may be negative. The material layer may have lower heat conductivity and/or approximately equivalent electrical resistance as TiAlN.
摘要:
Provided are phase change random access memory (PRAM) devices and methods of operating the same. The PRAM device may include a switching device, a lower electrode, a lower electrode contact layer, a phase change layer and/or an upper electrode. The lower electrode may be connected to a switching device. The lower electrode contact layer may be formed on the lower electrode. The phase change layer, which may include a bottom surface that contacts an upper surface of the lower electrode contact layer, may be formed on the lower electrode contact layer. The upper electrode may be formed on the phase change layer. The lower electrode contact layer may be formed of a material layer having an absolute value of a Seebeck coefficient higher than TiAlN. The Seebeck coefficient of the lower electrode contact layer may be negative. The material layer may have lower heat conductivity and/or approximately equivalent electrical resistance as TiAlN.