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1.发明申请Solution Process for Fabricating a Textured Transparent Conductive Oxide (TCO) 失效用于制造纹理透明导电氧化物（TCO）的溶液工艺公开(公告)号：US20120015147A1
公开(公告)日：2012-01-19
申请号：US12836300
申请日：2010-07-14
IPC分类号： B32B5/16 , F24J2/02 , B05D5/12 , H01L31/052
CPC分类号： H01L31/0236 , H01L31/1884 , Y02E10/50 , Y10T428/24413
摘要： A solution process is provided for forming a textured transparent conductive oxide (TCO) film. The process provides a substrate, and forms a first layer on the substrate of metal oxide nanoparticles such as ZnO, In2O3, or SnO2. The metal oxide nanoparticles have a faceted structure with an average size greater than 100 nanometers (nm). Voids between the metal oxide nanoparticles have a size about equal to the size of the metal oxide nanoparticles. Then, a second layer is formed overlaying the first layer, filling the voids between the nanoparticles of the first layer, and completely covering the substrate. The result is a continuous TCO film having an average surface roughness that is created by the combination of first and second layers.
摘要翻译： 提供了一种用于形成织构化的透明导电氧化物（TCO）膜的溶液方法。 该方法提供了一种衬底，并在诸如ZnO，In 2 O 3或SnO 2的金属氧化物纳米颗粒的衬底上形成第一层。 金属氧化物纳米颗粒具有平均尺寸大于100纳米（nm）的刻面结构。 金属氧化物纳米颗粒之间的空隙的尺寸大约等于金属氧化物纳米颗粒的尺寸。 然后，形成覆盖第一层的第二层，填充第一层的纳米颗粒之间的空隙，并完全覆盖基底。 结果是具有由第一层和第二层的组合产生的平均表面粗糙度的连续的TCO膜。
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公开(公告)号：US20100047476A1
公开(公告)日：2010-02-25
申请号：US12195673
申请日：2008-08-21
CPC分类号： C01B33/021
摘要： A Si nanoparticle precursor, precursor fabrication process, and precursor deposition process are presented. The method for forming a silicon (Si) nanoparticle precursor provides a plurality of nanoparticle classes, including at least one Si nanoparticle class. The nanoparticles in each nanoparticle class are defined as having a predetermined diameter. A predetermined amount of each nanoparticle class is measured and combined. For example, a first Si nanoparticle class may be provided having a largest diameter and a second Si nanoparticle class having a second-largest diameter equal to about (0.43)×(the largest diameter). As another example, Si nanoparticle classes may foe provided having a diameter ratio of about 77:32:17.
摘要翻译： 提出了Si纳米颗粒前体，前体制备工艺和前体沉积工艺。 形成硅（Si）纳米颗粒前体的方法提供多个纳米颗粒类别，包括至少一种Si纳米颗粒类。 每个纳米颗粒级中的纳米颗粒被定义为具有预定直径。 测量并组合每个纳米粒子类的预定量。 例如，可以提供具有最大直径的第一Si纳米颗粒类别和具有等于约（0.43）×（最大直径）的第二大直径的第二Si纳米颗粒类。 作为另一个实例，可以提供具有约77:32:17的直径比的Si纳米颗粒类。
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公开(公告)号：US08513720B2
公开(公告)日：2013-08-20
申请号：US12836217
申请日：2010-07-14
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02581 , H01L29/66969
摘要： A top gate and bottom gate thin film transistor (TFT) are provided with an associated fabrication method. The TFT is fabricated from a substrate, and an active metal oxide semiconductor (MOS) layer overlying the substrate. Source/drain (S/D) regions are formed in contact with the active MOS layer. A channel region is interposed between the S/D regions. The TFT includes a gate electrode, and a gate dielectric interposed between the channel region and the gate electrode. The active MOS layer may be ZnOx, InOx, GaOx, SnOx, or combinations of the above-mentioned materials. The active MOS layer also includes a primary dopant such as H, K, Sc, La, Mo, Bi, Ce, Pr, Nd, Sm, Dy, or combinations of the above-mentioned dopants. The active MOS layer may also include a secondary dopant.
摘要翻译： 顶栅和底栅薄膜晶体管（TFT）具有相关的制造方法。 TFT由衬底和覆盖衬底的活性金属氧化物半导体（MOS）层制成。 源极/漏极（S / D）区域形成为与有源MOS层接触。 沟道区域插入在S / D区域之间。 TFT包括栅极电极和介于沟道区域和栅电极之间的栅极电介质。 有源MOS层可以是ZnOx，InOx，GaOx，SnOx或上述材料的组合。 有源MOS层还包括主要掺杂剂如H，K，Sc，La，Mo，Bi，Ce，Pr，Nd，Sm，Dy或上述掺杂剂的组合。 有源MOS层还可以包括第二掺杂剂。
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4.发明授权Solution process for fabricating a textured transparent conductive oxide (TCO) 失效用于制造纹理透明导电氧化物（TCO）的溶液工艺公开(公告)号：US08404302B2
公开(公告)日：2013-03-26
申请号：US12836300
申请日：2010-07-14
CPC分类号： H01L31/0236 , H01L31/1884 , Y02E10/50 , Y10T428/24413
摘要： A solution process is provided for forming a textured transparent conductive oxide (TCO) film. The process provides a substrate, and forms a first layer on the substrate of metal oxide nanoparticles such as ZnO, In2O3, or SnO2. The metal oxide nanoparticles have a faceted structure with an average size greater than 100 nanometers (nm). Voids between the metal oxide nanoparticles have a size about equal to the size of the metal oxide nanoparticles. Then, a second layer is formed overlaying the first layer, filling the voids between the nanoparticles of the first layer, and completely covering the substrate. The result is a continuous TCO film having an average surface roughness that is created by the combination of first and second layers.
摘要翻译： 提供了一种用于形成织构化的透明导电氧化物（TCO）膜的溶液方法。 该方法提供了一种衬底，并在诸如ZnO，In 2 O 3或SnO 2的金属氧化物纳米颗粒的衬底上形成第一层。 金属氧化物纳米颗粒具有平均尺寸大于100纳米（nm）的刻面结构。 金属氧化物纳米颗粒之间的空隙的尺寸大约等于金属氧化物纳米颗粒的尺寸。 然后，形成覆盖第一层的第二层，填充第一层的纳米颗粒之间的空隙，并完全覆盖基底。 结果是具有由第一层和第二层的组合产生的平均表面粗糙度的连续的TCO膜。
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公开(公告)号：US20120012835A1
公开(公告)日：2012-01-19
申请号：US12836217
申请日：2010-07-14
IPC分类号： H01L29/786 , H01L21/34 , H01L21/336 , H01L29/12
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02581 , H01L29/66969
摘要： A top gate and bottom gate thin film transistor (TFT) are provided with an associated fabrication method. The TFT is fabricated from a substrate, and an active metal oxide semiconductor (MOS) layer overlying the substrate. Source/drain (S/D) regions are formed in contact with the active MOS layer. A channel region is interposed between the S/D regions. The TFT includes a gate electrode, and a gate dielectric interposed between the channel region and the gate electrode. The active MOS layer may be ZnOx, InOx, GaOx, SnOx, or combinations of the above-mentioned materials. The active MOS layer also includes a primary dopant such as H, K, Sc, La, Mo, Bi, Ce, Pr, Nd, Sm, Dy, or combinations of the above-mentioned dopants. The active MOS layer may also include a secondary dopant.
摘要翻译： 顶栅和底栅薄膜晶体管（TFT）具有相关的制造方法。 TFT由衬底和覆盖衬底的活性金属氧化物半导体（MOS）层制成。 源极/漏极（S / D）区域形成为与有源MOS层接触。 沟道区域插入在S / D区域之间。 TFT包括栅极电极和介于沟道区域和栅电极之间的栅极电介质。 有源MOS层可以是ZnOx，InOx，GaOx，SnOx或上述材料的组合。 有源MOS层还包括主要掺杂剂如H，K，Sc，La，Mo，Bi，Ce，Pr，Nd，Sm，Dy或上述掺杂剂的组合。 有源MOS层还可以包括第二掺杂剂。
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公开(公告)号：US08503064B2
公开(公告)日：2013-08-06
申请号：US13157225
申请日：2011-06-09
IPC分类号： G02B26/00
CPC分类号： G02F1/0128 , G02F1/13338 , G02F1/19 , G02F2001/13345 , G02F2203/10 , G02F2203/34 , G06F3/0412
摘要： An electrical pressure-sensitive reflective display includes an array of display pixels, each with a transparent top surface, first electrode, second electrode, an elastic polymer medium, and metallic nanoparticles distributed in the elastic polymer medium. When a first voltage potential is applied between the first and second electrodes of each display pixel, a first color is reflected from the incident spectrum of light, assuming no pressure is applied on the top surface of each display pixel. When the top surface of a first display pixel is deformed in response to an applied pressure, the elastic polymer medium in the first display pixel is compressed, decreasing the metallic nanoparticle-to-metallic nanoparticle mean distance in the first display pixel. In response to decreasing the metallic nanoparticle-to-metallic nanoparticle mean distance, the color reflected from the incident spectrum of light by the second display pixel is changed from the first color to second color.
摘要翻译： 电压敏反射显示器包括显示像素阵列，每个显示像素具有分布在弹性聚合物介质中的透明顶表面，第一电极，第二电极，弹性聚合物介质和金属纳米颗粒。 当在每个显示像素的第一和第二电极之间施加第一电压电位时，假设在每个显示像素的顶表面上没有施加压力，第一颜色从光的入射光谱反射。 当第一显示像素的顶表面响应于所施加的压力而变形时，第一显示像素中的弹性聚合物介质被压缩，从而降低第一显示像素中金属纳米颗粒与金属纳米颗粒的平均距离。 响应于减少金属纳米颗粒 - 金属纳米颗粒平均距离，由第二显示像素的入射光谱反射的颜色从第一颜色变为第二颜色。
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公开(公告)号：US08236631B2
公开(公告)日：2012-08-07
申请号：US12644061
申请日：2009-12-22
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译： 提供了一个四晶体管施密特触发器。 施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极， 背栅极和源极/漏极区域。 （常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。 （传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。
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8.发明授权公开(公告)号：US08045107B2
公开(公告)日：2011-10-25
申请号：US12614368
申请日：2009-11-06
IPC分类号： G02F1/1335 , G02B26/00 , H01L21/00
CPC分类号： G02F1/195 , G02F2203/10
摘要： A color-tunable plasmonic device is provided with a partially modulated refractive index. A first dielectric layer overlies a bottom electrode, and has a refractive index non-responsive to an electric field. A second dielectric layer overlies the first dielectric layer, having a refractive index responsive to an electric field. An electrically conductive top electrode overlies the second dielectric layer. A plasmonic layer including a plurality of discrete plasmonic particles is interposed between the top and bottom electrodes. In one aspect, the plasmonic layer is interposed between the first and second dielectric layers. In a second aspect, the plasmonic layer is interposed between the first dielectric layer and the bottom electrode. In a third aspect, a first plasmonic layer is interposed between the first dielectric layer and the bottom electrode, and a second plasmonic layer of discrete plasmonic particles is interposed between the first dielectric layer and the second dielectric layer.
摘要翻译： 彩色等离子体激元器件具有部分调制的折射率。 第一电介质层覆盖在底部电极上，并且具有对电场无响应的折射率。 第二电介质层覆盖第一电介质层，具有响应于电场的折射率。 导电顶电极覆盖在第二电介质层上。 包括多个离散等离子体激元的等离子体激元层插入在顶部和底部电极之间。 在一个方面，等离子体激元层介于第一和第二电介质层之间。 在第二方面，等离子体激元层介于第一介电层和底电极之间。 在第三方面中，在第一介电层和底电极之间插入第一等离子体激元层，并且在第一介电层和第二电介质层之间插入离散等离子体激元的第二等离子体层。
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公开(公告)号：US20110109821A1
公开(公告)日：2011-05-12
申请号：US12635349
申请日：2009-12-10
IPC分类号： G02F1/133
CPC分类号： G02F1/23 , G02F2203/10 , G02F2203/34
摘要： A plasmonic display device is provided with liquid crystal dipole molecule control. The device is made from a first set of electrodes including at least one electrically conductive top electrode and at least one electrically conductive bottom electrode capable of generating a first electric field in a first direction. A second set of electrodes, including an electrically conductive right electrode and an electrically conductive left electrode, is capable of generating a second electric field in a second first direction. A dielectric layer overlies the bottom electrode, made from a liquid crystal material with molecules having dipoles responsive to an electric field. A plasmonic layer, including a plurality of discrete plasmonic particles, is interposed between the first and second set of electrodes and in contact with the dielectric layer. In one aspect, the plasmonic layer is embedded in the dielectric layer.
摘要翻译： 具有液晶偶极子分子控制的等离子体显示装置。 该装置由第一组电极制成，其包括至少一个导电顶电极和能够沿第一方向产生第一电场的至少一个导电底电极。 包括导电右电极和导电左电极的第二组电极能够在第二第一方向上产生第二电场。 电介质层覆盖在液晶材料制成的底部电极上，分子具有响应于电场的偶极子。 包括多个离散等离子体激元的等离子体激元层介于第一和第二组电极之间并与电介质层接触。 在一个方面，等离子体激元层嵌入电介质层。
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公开(公告)号：US07872309B2
公开(公告)日：2011-01-18
申请号：US12140017
申请日：2008-06-16
IPC分类号： H01L27/12 , H01L29/786
CPC分类号： H01L29/78621 , H01L29/66621 , H01L29/66757 , H01L29/78627
摘要： A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.
摘要翻译： 提供了具有自对准轻掺杂漏极（LDD）的凹入栅极薄膜晶体管（RG-TFT）以及相应的制造方法。 该方法沉积覆盖衬底的绝缘体并蚀刻绝缘体中的沟槽。 沟槽有一个底部和侧壁。 在绝缘体和沟槽上形成有源硅（Si）层，在有源Si层上方形成栅极氧化层。 然后在沟槽中形成凹陷栅电极。 TFT是掺杂的，并且LDD区域形成在覆盖沟槽侧壁的有源Si层中。 LDD区域具有从沟槽侧壁的顶部延伸到沟槽底部的长度，其掺杂密度响应于LDD长度而减小。 替代地，LDD长度与沟槽的深度直接相关。
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