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14 条记录 (耗时 0.019 秒)

    System and method for detecting the width of a data bus
    1.
    发明申请
    System and method for detecting the width of a data bus 有权
    用于检测数据总线宽度的系统和方法

    公开(公告)号：US20050180206A1

    公开(公告)日：2005-08-18

    申请号：US11048761

    申请日：2005-02-03

    申请人： Jerrold Randell ,  Richard Madter ,  Wei Huang

    发明人： Jerrold Randell ,  Richard Madter ,  Wei Huang

    IPC分类号： G06F13/00 ,  G06F13/16 ,  G11C11/34

    CPC分类号： G06F13/1678 ,  G06F13/1694

    摘要： A device employs a method for determining the data bus width of a non-volatile memory, such as NAND flash memory. The method performs at least two read operations on the non-volatile memory so as to test the changing of selected data bits. The method may be performed such that weak pull down and pull up operations are performed to test the data outputs of the non-volatile memory.

    摘要翻译： 一种器件采用一种用于确定诸如NAND闪存之类的非易失性存储器的数据总线宽度的方法。 该方法对非易失性存储器执行至少两次读取操作，以便测试所选数据位的改变。 可以执行该方法，使得执行弱下拉和上拉操作以测试非易失性存储器的数据输出。

    On-chip storage, creation, and manipulation of an encryption key
    2.
    发明申请
    On-chip storage, creation, and manipulation of an encryption key 有权
    加密密钥的片上存储，创建和操作

    公开(公告)号：US20050232415A1

    公开(公告)日：2005-10-20

    申请号：US11051560

    申请日：2005-02-04

    申请人： Herbert Little ,  Jerrold Randell ,  Richard Madter ,  Ryan Hickey ,  Andrew Fergusson

    发明人： Herbert Little ,  Jerrold Randell ,  Richard Madter ,  Ryan Hickey ,  Andrew Fergusson

    IPC分类号： G06F12/14 ,  G06F21/00 ,  H04K1/00 ,  H04L9/00 ,  H04L9/08 ,  H04L9/14 ,  H04L9/32

    CPC分类号： G06F21/64 ,  G06F12/1408 ,  G06F21/72 ,  G06F21/79 ,  G06F21/85 ,  H04L9/0863 ,  H04L9/0869 ,  H04L9/0891 ,  H04L9/0894 ,  Y02D10/13

    摘要： A system and method of creating and managing encryption keys in a data processing device generates subsequent encryption keys by combining the existing encryption key with an existing password and seed value. In the preferred embodiment, the initial encryption key is embedded during manufacture and is unknown to the user and manufacturer, thus ensuring that all subsequent encryption keys are derived from an unknown value. When a subsequent encryption key is generated, all data encrypted using the existing encryption key is decrypted using the existing encryption key and re-encrypted using the subsequent encryption key before the existing encryption key is overwritten. In a further aspect, during encryption/decryption the encryption key is combined with the sector address of the data to be encrypted/decrypted in order to generate a unique key for each sector of data to be encrypted/decrypted.

    摘要翻译： 在数据处理设备中创建和管理加密密钥的系统和方法通过将现有加密密钥与现有密码和种子值组合来生成后续加密密钥。 在优选实施例中，初始加密密钥在制造期间被嵌入，并且对于用户和制造商来说是未知的，因此确保所有后续加密密钥都是从未知值导出的。 当生成随后的加密密钥时，使用现有加密密钥加密的所有数据使用现有的加密密钥进行解密，并且在覆盖现有加密密钥之前使用随后的加密密钥重新加密。 在另一方面，在加密/解密期间，将加密密钥与要加密/解密的数据的扇区地址组合，以便为每个要加密/解密的数据扇区生成唯一的密钥。

    Memory controller interface
    3.
    发明申请
    Memory controller interface 有权
    内存控制器界面

    公开(公告)号：US20050185472A1

    公开(公告)日：2005-08-25

    申请号：US11051491

    申请日：2005-02-04

    申请人： Jerrold Randell ,  Richard Madter ,  Karin Werder

    发明人： Jerrold Randell ,  Richard Madter ,  Karin Werder

    IPC分类号： G06F9/44 ,  G06F12/02 ,  G06F12/08 ,  G06F12/16 ,  G11C16/04

    CPC分类号： G06F12/0893 ,  G06F11/1068 ,  G06F11/1441 ,  G06F11/2015 ,  G06F12/0638 ,  G06F12/1441 ,  G06F21/79 ,  G06F2212/2022

    摘要： A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and SRAM memory devices to instead operate using NAND flash and SDRAM. The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed by the processor as though it were accessing data from NOR flash/SRAM. Sectors containing data required by the processor are read out of NAND flash and written into SDRAM, where the data can be randomly accessed by the processor.

    摘要翻译： 一种存储器接口控制器和方法，其允许处理器设计和配置为与NOR闪存和SRAM存储器件一起操作，以代替使用NAND闪存和SDRAM进行操作。 该系统通过将NAND闪存中的扇区缓存到SDRAM中来实现，其中数据可以被处理器随机访问，就像它正在从NOR闪存/ SRAM访问数据一样。 包含处理器所需数据的扇区从NAND闪存中读出并写入SDRAM，数据可由处理器随机访问。

    Debugging port security interface
    4.
    发明申请
    Debugging port security interface 有权
    调试端口安全接口

    公开(公告)号：US20050193220A1

    公开(公告)日：2005-09-01

    申请号：US11049987

    申请日：2005-02-04

    申请人： Herbert Little ,  Jerrold Randell ,  Richard Madter ,  Ryan Hickey

    发明人： Herbert Little ,  Jerrold Randell ,  Richard Madter ,  Ryan Hickey

    IPC分类号： G06F11/36 ,  G06F12/14 ,  H04L9/00

    CPC分类号： G06F21/79 ,  G06F11/3656 ,  G06F2221/2105

    摘要： The present invention provides a secure JTAG interface to an application-specific integrated circuit (ASIC). In the preferred embodiment the invention operates through the combined efforts of a Security Module (SM) comprising a state machine that controls the security modes for the ASIC, and a Test Control Module (TCM) which contains the JTAG interface. The TCM operates in either a restricted mode or an unrestricted mode, depending on the state of the SM state machine. In a restricted mode, only limited access to memory content is permitted. In an unrestricted mode, full access to memory content is permitted.

    摘要翻译： 本发明提供了一种用于专用集成电路（ASIC）的安全JTAG接口。 在优选实施例中，本发明通过包括控制ASIC的安全模式的状态机和包含JTAG接口的测试控制模块（TCM）的安全模块（SM）的组合进行操作。 根据SM状态机的状态，TCM以受限制模式或非限制模式运行。 在限制模式下，只允许对存储器内容的访问有限。 在无限制模式下，允许完全访问内存内容。

    System and method for managing battery slump during wireless communications using signal triggered voltage monitoring
    5.
    发明授权
    System and method for managing battery slump during wireless communications using signal triggered voltage monitoring 有权
    使用信号触发电压监测在无线通信期间管理电池坍落度的系统和方法

    公开(公告)号：US08032189B2

    公开(公告)日：2011-10-04

    申请号：US11549762

    申请日：2006-10-16

    申请人： Martin Guthrie ,  Richard Madter ,  Dusan Veselic ,  Christopher Book ,  Kent Nickerson

    发明人： Martin Guthrie ,  Richard Madter ,  Dusan Veselic ,  Christopher Book ,  Kent Nickerson

    IPC分类号： H04B1/38

    CPC分类号： G06F1/3203 ,  G06F1/305 ,  H01M10/48

    摘要： A system and method for managing battery slump in a battery-powered communications device including: an input configured for receiving battery voltage level information; an output configured for sending a signal for terminating a transmission; and a controller connected to the input and the output and configured to receive the battery voltage level information from the input; monitor the battery voltage level information; and send a signal via the output to terminate a transmission if the battery voltage level information crosses a predetermined threshold during the transmission. In particular, the system and method may further include an input connected to the controller and configured for receiving a signal indicating when a transmission is beginning or occurring and the controller is further configured to receive and monitor the battery voltage level information only when the transmission is occurring.

    摘要翻译： 一种用于在电池供电的通信设备中管理电池坍落度的系统和方法，包括：被配置为接收电池电压电平信息的输入; 被配置为发送用于终止传输的信号的输出; 以及控制器，其连接到所述输入和所述输出并且被配置为从所述输入接收所述电池电压电平信息; 监控电池电压等级信息; 并且如果在传输期间电池电压电平信息跨越预定阈值，则通过输出发送信号以终止传输。 具体地，该系统和方法还可以包括连接到控制器并被配置用于接收指示何时发生开始或发生的信号的控制器，并且该控制器进一步被配置为仅在该传输是 发生。

    CACHE OPERATION WITH NON-CACHE MEMORY
    6.
    发明申请
    CACHE OPERATION WITH NON-CACHE MEMORY 有权
    使用非高速缓存存储器进行缓存操作

    公开(公告)号：US20080016283A1

    公开(公告)日：2008-01-17

    申请号：US11860159

    申请日：2007-09-24

    申请人： Richard Madter

    发明人： Richard Madter

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0888 ,  G06F12/0891 ,  G06F2212/2022

    摘要： A system and method are provided for bypassing cache memory when reading data from system memory particularly when the primary memory could include memory types where the read operation mixes non-data with data. A system and method are provided for bypassing and invalidating cache memory when writing data to system memory particularly when the primary memory could include memory types where the write operation mixes non-data with data.

    摘要翻译： 提供了一种用于在从系统存储器读取数据时绕过高速缓冲存储器的系统和方法，特别是当主存储器可以包括读取操作将非数据与数据混合的存储器类型时。 提供了一种系统和方法，用于在将数据写入系统存储器时绕过和无效高速缓冲存储器，特别是当主存储器可能包括写操作将非数据与数据混合在一起的存储器类型时。

    Cache operation with non-cache memory
    9.
    发明申请
    Cache operation with non-cache memory 有权
    缓存操作与非缓存内存

    公开(公告)号：US20070094451A1

    公开(公告)日：2007-04-26

    申请号：US11603799

    申请日：2006-11-22

    申请人： Richard Madter

    发明人： Richard Madter

    IPC分类号： G06F13/00 ,  G06F12/00

    CPC分类号： G06F12/0888 ,  G06F12/0891 ,  G06F2212/2022

    摘要： A system and method are provided for bypassing cache memory when reading data from system memory particularly when the primary memory could include memory types where the read operation mixes non-data with data. A system and method are provided for bypassing and invalidating cache memory when writing data to system memory particularly when the primary memory could include memory types where the write operation mixes non-data with data.

    摘要翻译： 提供了一种用于在从系统存储器读取数据时绕过高速缓冲存储器的系统和方法，特别是当主存储器可以包括读取操作将非数据与数据混合的存储器类型时。 提供了一种系统和方法，用于在将数据写入系统存储器时绕过和无效高速缓冲存储器，特别是当主存储器可能包括写操作将非数据与数据混合在一起的存储器类型时。

    On-chip security method and apparatus
    10.
    发明申请
    On-chip security method and apparatus 有权
    片上安全方法和装置

    公开(公告)号：US20050033951A1

    公开(公告)日：2005-02-10

    申请号：US10500131

    申请日：2002-12-13

    申请人： Richard Madter ,  Ryan Hickey ,  Christopher Pattenden

    发明人： Richard Madter ,  Ryan Hickey ,  Christopher Pattenden

    IPC分类号： G06F21/00 ,  G06F15/177

    CPC分类号： G06F21/71 ,  G06F21/575 ,  G06F21/73

    摘要： A boot method an apparatus arc described which reduce the likelihood of a security breach in a mobile device, preferably in a situation where a reset has been initiated. A predetermined security value, or password, is stored, for example in BootROM. A value of a security location within FLASH memory is read and the two values are compared. Polling of the serial port is selectively performed, depending on the result of such comparison. In a presently preferred embodiment, if the value in the security location matches the predetermined security value, then polling of the serial port is nut performed. This reduces potential security breaches caused in conventional arrangements where code may be downloaded from the serial port and executed, which allows anyone to access and upload programs and data in the FLASH memory, including confidential and proprietary information.

    摘要翻译： 描述了引导方法，其优选地在已经启动复位的情况下降低了移动设备中安全漏洞的可能性。 存储预定的安全值或密码，例如在BootROM中。 读取FLASH存储器中的安全位置的值，并比较两个值。 根据这种比较的结果，选择性地执行串口的轮询。 在当前优选的实施例中，如果安全位置中的值与预定的安全值相匹配，则进行螺母的轮询。 这减少了常规安排导致的潜在安全漏洞，其中代码可以从串行端口下载并执行，这允许任何人访问和上传FLASH存储器中的程序和数据，包括机密和专有信息。