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    Methods of forming non-volatile memory devices having floating gate electrodes
    4.
    发明授权
    Methods of forming non-volatile memory devices having floating gate electrodes 失效
    形成具有浮动栅电极的非易失性存储器件的方法

    公开(公告)号：US07445997B2

    公开(公告)日：2008-11-04

    申请号：US11103069

    申请日：2005-04-11

    申请人： Won-Jun Lee ,  Tae-Hyun Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Byoung-Moon Yoon ,  Ji-Hong Kim

    发明人： Won-Jun Lee ,  Tae-Hyun Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Byoung-Moon Yoon ,  Ji-Hong Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Methods of forming non-volatile memory devices include the steps of forming a semiconductor substrate having first and second floating gate electrodes thereon and an electrically insulating region extending between the first and second floating gate electrodes. A step is then performed to etch back the electrically insulating region to expose upper corners of the first and second floating gate electrodes. Another etching step is then performed. This etching step includes exposing upper surfaces and the exposed upper corners of the first and second floating gate electrodes to an etchant that rounds the exposed upper corners of the first and second floating gate electrodes. The step of etching back the electrically insulating region includes etching back the electrically insulating region to expose sidewalls of the first and second floating gate electrodes having heights ranging from about 30 Å to about 200 Å. The step of exposing the upper corners of the first and second floating gate electrodes to an etchant is followed by the step of etching back the electrically insulating region to expose entire sidewalls of the first and second floating gate electrodes.

    摘要翻译： 形成非易失性存储器件的方法包括以下步骤：在其上形成具有第一和第二浮栅的半导体衬底和在第一和第二浮栅之间延伸的电绝缘区。 然后执行步骤以回蚀电绝缘区域以暴露第一和第二浮栅电极的上角。 然后执行另一蚀刻步骤。 该蚀刻步骤包括将第一和第二浮栅电极的上表面和暴露的上角露出到蚀刻剂，该蚀刻剂围绕第一和第二浮栅的暴露的上角。 蚀刻回电绝缘区域的步骤包括蚀刻电绝缘区域以暴露第一和第二浮栅电极的侧壁，其高度范围为约至约200。 将第一和第二浮栅的上角暴露于蚀刻剂的步骤之后是蚀刻电绝缘区以暴露第一和第二浮栅的整个侧壁的步骤。

    Parallel distributed sample descrambling apparatus of passive optical network and method thereof
    5.
    发明授权
    Parallel distributed sample descrambling apparatus of passive optical network and method thereof 有权
    无源光网络并行分布式采样解扰装置及其方法

    公开(公告)号：US07206945B2

    公开(公告)日：2007-04-17

    申请号：US10317186

    申请日：2002-12-12

    申请人： Ji-Hong Kim

    发明人： Ji-Hong Kim

    IPC分类号： H04K9/00

    CPC分类号： H04L25/03872

    摘要： Disclosed is a parallel distributed sample descrambling (DSS) apparatus and a method that lowers a clock speed of 622 MHz into ⅛ speed (77.76 MHz) and operates a serial descrambling processing in unit of bit by converting the processing into a parallel descrambling processing in unit of byte, power consumption can thus be reduced and a sufficient timing margin can be secured. The parallel DSS apparatus includes a serial-parallel conversion unit for converting receiving data into parallel data (D[7:0]) and generating a counter signal, a header error check (hereinafter, as HEC) generation unit for generating HEC data of the receiving data by CRC calculation, and abstracting upper two bits of the HEC data, and a descrambling processing unit for performing parallel descrambling of byte module by receiving output signals of the serial-parallel conversion unit and the HEC generation unit.

    摘要翻译： 公开了一种并行分布式采样解扰（DSS）装置和一种将622MHz的时钟速度降至1/8速度（77.76MHz）的方法，并且通过将处理转换为并行解扰处理来操作以比特为单位的串行解扰处理 以字节为单位，因此可以降低功耗并且可以确保足够的时序余量。 并行DSS装置包括：串行并行转换单元，用于将接收数据转换成并行数据（D [7：0]）并产生计数器信号，头部错误检查（以下称为HEC）生成单元，用于生成HEC数据 通过CRC计算接收数据，以及抽取HEC数据的高两位;以及解扰处理单元，用于通过接收串行 - 并行转换单元和HEC生成单元的输出信号来执行字节模块的并行解扰。

    Method of manufacturing a semiconductor device
    6.
    发明申请
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20060088987A1

    公开(公告)日：2006-04-27

    申请号：US11249515

    申请日：2005-10-14

    申请人： In-Joon Yeo ,  Won-Jun Lee ,  Tae-Hyun Kim ,  Ji-Hong Kim ,  Byoung-Moon Yoon

    发明人： In-Joon Yeo ,  Won-Jun Lee ,  Tae-Hyun Kim ,  Ji-Hong Kim ,  Byoung-Moon Yoon

    IPC分类号： H01L21/20

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A method of manufacturing a semiconductor device includes forming an insulation pattern over a substrate. The insulation pattern has at least one opening that exposes a surface of the substrate. Then, a first polysilicon layer is formed over the substrates such that the first polysilicon layer fills the opening. The first polysilicon layer also includes a void therein. An upper portion of the first polysilicon layer is removed such that void expands to a recess and the recess is exposed. A second polysilicon layer is formed over the substrate such that the second polysilicon layer fills the recess.

    摘要翻译： 制造半导体器件的方法包括在衬底上形成绝缘图案。 绝缘图案具有暴露基板表面的至少一个开口。 然后，在基板上形成第一多晶硅层，使得第一多晶硅层填充开口。 第一多晶硅层还包括空隙。 去除第一多晶硅层的上部，使得空隙膨胀到凹部并且凹部暴露。 第二多晶硅层形成在衬底上，使得第二多晶硅层填充凹部。

    Methods of forming non-volatile memory devices having floating gate electrodes
    7.
    发明申请
    Methods of forming non-volatile memory devices having floating gate electrodes 失效
    形成具有浮动栅电极的非易失性存储器件的方法

    公开(公告)号：US20050255654A1

    公开(公告)日：2005-11-17

    申请号：US11103069

    申请日：2005-04-11

    申请人： Won-Jun Lee ,  Tae-Hyun Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Byoung-Moon Yoon ,  Ji-Hong Kim

    发明人： Won-Jun Lee ,  Tae-Hyun Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Byoung-Moon Yoon ,  Ji-Hong Kim

    IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Methods of forming non-volatile memory devices include the steps of forming a semiconductor substrate having first and second floating gate electrodes thereon and an electrically insulating region extending between the first and second floating gate electrodes. A step is then performed to etch back the electrically insulating region to expose upper corners of the first and second floating gate electrodes. Another etching step is then performed. This etching step includes exposing upper surfaces and the exposed upper corners of the first and second floating gate electrodes to an etchant that rounds the exposed upper corners of the first and second floating gate electrodes. The step of etching back the electrically insulating region includes etching back the electrically insulating region to expose sidewalls of the first and second floating gate electrodes having heights ranging from about 30 Å to about 200 Å. The step of exposing the upper corners of the first and second floating gate electrodes to an etchant is followed by the step of etching back the electrically insulating region to expose entire sidewalls of the first and second floating gate electrodes.

    摘要翻译： 形成非易失性存储器件的方法包括以下步骤：在其上形成具有第一和第二浮栅的半导体衬底和在第一和第二浮栅之间延伸的电绝缘区。 然后执行步骤以回蚀电绝缘区域以暴露第一和第二浮栅电极的上角。 然后执行另一蚀刻步骤。 该蚀刻步骤包括将第一和第二浮栅电极的上表面和暴露的上角露出到蚀刻剂，该蚀刻剂围绕第一和第二浮栅的暴露的上角。 蚀刻回电绝缘区域的步骤包括蚀刻电绝缘区域以暴露第一和第二浮栅电极的侧壁，其高度范围为约至约200。 将第一和第二浮栅的上角暴露于蚀刻剂的步骤之后是蚀刻电绝缘区以暴露第一和第二浮栅的整个侧壁的步骤。

    Method of manufacturing a semiconductor device having voids in a polysilicon layer
    8.
    发明授权
    Method of manufacturing a semiconductor device having voids in a polysilicon layer 有权
    制造在多晶硅层中具有空隙的半导体器件的方法

    公开(公告)号：US07582559B2

    公开(公告)日：2009-09-01

    申请号：US11249515

    申请日：2005-10-14

    申请人： In-Joon Yeo ,  Won-Jun Lee ,  Tae-Hyun Kim ,  Ji-Hong Kim ,  Byoung-Moon Yoon

    发明人： In-Joon Yeo ,  Won-Jun Lee ,  Tae-Hyun Kim ,  Ji-Hong Kim ,  Byoung-Moon Yoon

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A method of manufacturing a semiconductor device includes forming an insulation pattern over a substrate. The insulation pattern has at least one opening that exposes a surface of the substrate. Then, a first polysilicon layer is formed over the substrates such that the first polysilicon layer fills the opening. The first polysilicon layer also includes a void therein. An upper portion of the first polysilicon layer is removed such that void expands to a recess and the recess is exposed. A second polysilicon layer is formed over the substrate such that the second polysilicon layer fills the recess.

    摘要翻译： 制造半导体器件的方法包括在衬底上形成绝缘图案。 绝缘图案具有暴露基板表面的至少一个开口。 然后，在基板上形成第一多晶硅层，使得第一多晶硅层填充开口。 第一多晶硅层还包括空隙。 去除第一多晶硅层的上部，使得空隙膨胀到凹部并且凹部暴露。 第二多晶硅层形成在衬底上，使得第二多晶硅层填充凹部。

    Etching solution, method of forming a pattern using the same, method of manufacturing a multiple gate oxide layer using the same and method of manufacturing a flash memory device using the same
    9.
    发明授权
    Etching solution, method of forming a pattern using the same, method of manufacturing a multiple gate oxide layer using the same and method of manufacturing a flash memory device using the same 失效
    蚀刻溶液，使用其形成图案的方法，使用该方法制造多栅极氧化物层的方法以及使用其制造闪存器件的方法

    公开(公告)号：US07579284B2

    公开(公告)日：2009-08-25

    申请号：US11482773

    申请日：2006-07-10

    申请人： Byoung-Moon Yoon ,  Ji-Hong Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim

    发明人： Byoung-Moon Yoon ,  Ji-Hong Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim

    IPC分类号： H01L21/311

    CPC分类号： C09K13/04 ,  H01L21/32134

    摘要： Example embodiments of the present invention relate to an etching solution, a method of forming a pattern using the same, a method of manufacturing a multiple gate oxide layer using the same and a method of manufacturing a flash memory device using the same. Other example embodiments of the present invention relate to an etching solution having an etching selectivity between a polysilicon layer and an oxide layer, a method of forming a pattern using an etching solution using the same, a method of manufacturing a multiple gate oxide layer using the same, and a method of manufacturing a flash memory device using the same. An etching solution including hydrogen peroxide (H2O2) and ammonium hydroxide (NH4OH) by a volume ratio of about 1:2 to about 1:10 mixed in water. In a method of forming a pattern and methods of manufacturing a multiple gate oxide layer and a flash memory device, a polysilicon layer may be formed on a substrate. An insulation layer pattern including an opening exposing the polysilicon layer may be formed on the polysilicon layer. The polysilicon layer exposed by the insulation layer pattern may be etched using the etching solution. A polysilicon layer pattern may be formed on the substrate using the etching solution.

    摘要翻译： 本发明的示例性实施例涉及一种蚀刻溶液，使用该方法形成图案的方法，使用该蚀刻溶液的多栅极氧化物层的制造方法以及使用其制造闪存器件的方法。 本发明的其它示例性实施例涉及在多晶硅层和氧化物层之间具有蚀刻选择性的蚀刻溶液，使用其使用蚀刻溶液形成图案的方法，使用该栅极氧化物层的方法 以及使用其制造闪存器件的方法。 包含在水中混合的体积比为约1:2至约1:10的过氧化氢（H 2 O 2）和氢氧化铵（NH 4 OH）的蚀刻溶液。 在形成图案的方法和制造多栅极氧化物层和闪存器件的方法中，可以在衬底上形成多晶硅层。 可以在多晶硅层上形成包括露出多晶硅层的开口的绝缘层图案。 可以使用蚀刻溶液蚀刻由绝缘层图案暴露的多晶硅层。 可以使用蚀刻溶液在衬底上形成多晶硅层图案。

    Copolymer useful for positive photoresist and chemical amplification positive photoresist composition comprising the same
    10.
    发明授权
    Copolymer useful for positive photoresist and chemical amplification positive photoresist composition comprising the same 失效
    用于正性光致抗蚀剂的共聚物和包含其的化学扩增正性光致抗蚀剂组合物

    公开(公告)号：US5989775A

    公开(公告)日：1999-11-23

    申请号：US998546

    申请日：1997-12-26

    申请人： Joo-Hyeon Park ,  Ji-Hong Kim ,  Ki-Dae Kim ,  Sun-Yi Park ,  Seong-Ju Kim

    发明人： Joo-Hyeon Park ,  Ji-Hong Kim ,  Ki-Dae Kim ,  Sun-Yi Park ,  Seong-Ju Kim

    IPC分类号： G03F7/004 ,  G03F7/039 ,  H01L21/027

    CPC分类号： G03F7/039 ,  G03F7/0045 ,  Y10S430/106

    摘要： A copolymer having a repeating unit represented by the following general formula I and a chemical amplification positive photoresist composition having the copolymer and a photoacid generator. The photoresist can allow for a good pattern shape even though a post-baking is taken in a somewhat delayed time and for a use of any radiation, such as uv light, deep uv light and charged particle beam. Also, it is superior in storage stability and resolution so that it is useful for the high integration of semiconductor devices. The polymer ranges, in polystyrene-reduced average molecular weight, from 1,000 to 1,000,000. The polymer is represented by the following repeating pattern: ##STR1## wherein, R.sub.1, R.sub.2 and R.sub.3 independently represent a hydrogen atom or a methyl; R.sub.4, R.sub.5 and R.sub.6 independently represent a hydrogen atom, an alkyl group, an alkoxy group or a halogen; 1, m, n each is a repeating number satisfying the condition that 0.3

    摘要翻译： 具有由以下通式I表示的重复单元的共聚物和具有共聚物和光致酸发生剂的化学扩增正性光致抗蚀剂组合物。 即使在稍微延迟的时间内进行后烘烤并且使用诸如紫外光，深紫外光和带电粒子束的任何辐射，光致抗蚀剂可以允许良好的图案形状。 此外，它在存储稳定性和分辨率方面是优异的，因此它对于半导体器件的高集成是有用的。 聚苯乙烯换算的聚合物的平均分子量为1,000至1,000,000。 聚合物由以下重复图案表示：其中，R1，R2和R3独立地表示氢原子或甲基; R4，R5和R6独立地表示氢原子，烷基，烷氧基或卤素; 1，m，n分别为满足0.3 <1 /（m + n）<0.9,0.1