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    Instruction generator architecture for a video signal processor controller
    2.
    发明授权
    Instruction generator architecture for a video signal processor controller 失效
    视频信号处理器控制器的指令生成器架构

    公开(公告)号：US5210836A

    公开(公告)日：1993-05-11

    申请号：US421500

    申请日：1989-10-13

    申请人： Jim Childers ,  Peter Reinecke ,  Moo-Taek Chung ,  Hiroshi Miyaguchi

    发明人： Jim Childers ,  Peter Reinecke ,  Moo-Taek Chung ,  Hiroshi Miyaguchi

    IPC分类号： F02B75/02 ,  G06F15/80 ,  G06T1/20

    CPC分类号： G06T1/20 ,  G06F15/8007 ,  F02B2075/027

    摘要： A synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and is capable of real-time digital processing of video signals. In video applications a data input control circuit including a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit is provided.

    摘要翻译： 具有以线性阵列组织的多个一位处理器元件的同步矢量处理器（SVP）装置。 处理器元件都由序列发生器，状态机或控制电路（控制器）共同控制，以使得能够作为并行处理装置进行操作。 每个处理器元件包括一组输入寄存器，两组寄存器文件，一组工作寄存器，包括一位全加器/减法器的算术逻辑单元和一组输出寄存器。 在视频应用中，每个处理器元件在水平扫描线的一个像素上操作，并且能够对视频信号进行实时数字处理。 在视频应用中，提供了包括主控制器电路，垂直定时发生器电路，恒定发电机电路，水平定时发生器电路和指令发生器电路的数据输入控制电路。

    Sequential constant generator system for indicating the last data word by using the end of loop bit having opposite digital state than other data words
    3.
    发明授权
    Sequential constant generator system for indicating the last data word by using the end of loop bit having opposite digital state than other data words 失效
    顺序常数发生器系统，用于通过使用与其他数据字相反的数字状态的循环位的结尾来指示最后的数据字

    公开(公告)号：US5452425A

    公开(公告)日：1995-09-19

    申请号：US163606

    申请日：1993-12-07

    申请人： Jim Childers ,  Hiroshi Miyaguchi ,  Peter Reinecke

    发明人： Jim Childers ,  Hiroshi Miyaguchi ,  Peter Reinecke

    IPC分类号： F02B75/02 ,  G06F15/80 ,  G06F9/26 ,  G06F9/06

    CPC分类号： G06F15/8092 ,  F02B2075/027

    摘要： A constant generator is described which provides a sequence of digital constants in a synchronous vector processor. The constant generator includes a constant loop memory for storing data words organized into a plurality of data constant patterns and an end of loop bit, a constant loop counter for supplying sequential addresses to the constant loop memory, and a constant loop counter controller for loading the counter with one of a set of predetermined starting addresses associated with a desired constant pattern stored in the constant loop memory. Additionally, a method of supplying a sequence of digital constants in said constant generator is disclosed and includes the steps of storing a plurality of data words in a plurality of constant patterns, where each constant pattern includes an end of loop bit, supplying an address to the constant loop memory and supplying sequential addresses to the constant loop memory.

    摘要翻译： 描述了在同步向量处理器中提供数字常数序列的常数发生器。 常数发生器包括用于存储组织成多个数据常数模式和循环位结束的数据字的恒定循环存储器，用于向恒定循环存储器提供顺序地址的常数循环计数器和用于加载 计数器与存储在恒定循环存储器中的期望常数模式相关联的一组预定起始地址中的一个。 另外，公开了一种在所述常数发生器中提供数字常数序列的方法，包括以多个恒定模式存储多个数据字的步骤，其中每个常数模式包括循环位结束，向 恒定循环存储器，并向恒定循环存储器提供顺序地址。

    Electronic circuit for reducing controller memory requirements
    4.
    发明授权
    Electronic circuit for reducing controller memory requirements 失效
    减少控制器内存要求的电子电路

    公开(公告)号：US5680600A

    公开(公告)日：1997-10-21

    申请号：US484117

    申请日：1995-06-07

    申请人： Jim Childers ,  Peter Reinecke

    发明人： Jim Childers ,  Peter Reinecke

    IPC分类号： G06F9/32 ,  G06F15/80 ,  G06F9/26

    CPC分类号： G06F9/325 ,  G06F15/8007

    摘要： An electronic circuit has reduced controller memory requirements for multiple sequential instructions. The electronic circuit includes: a controller memory (1258) with addressable storage locations; a program counter (1548); control logic (1586) for receiving control information from an addressable storage location of the controller memory for performing logical operations on the control information and generating a control signal (1609) responsive to the control information; a repeat counter (1294) for receiving a repeat instruction signal from the controller memory (1258) and for sending a hold count signal (1233) to the program counter (1584) and the control logic (1586) such that the program counter (1584) continues to select the same addressable storage location and the control logic (586) repeats sending the control signal (1609); and a register address counter (1290) for receiving the control signal from the control logic (1586), the hold count signal (1233) from the repeat counter (1294) and a register address signal (1604) from the controller memory. The register address signal stored in the register address counter (1290) points to one of a plurality of registers. The register address counter (1290) receives and stores the address signal if the repeat counter (1294) fail to send the hold count signal and increments the register address signal to point to a next consecutive register if the repeat counter (1294) sends the hold count signal.

    摘要翻译： 电子电路减少了多个顺序指令的控制器存储器要求。 电子电路包括：具有可寻址存储位置的控制器存储器（1258） 程序计数器（1548）; 控制逻辑（1586），用于从所述控制器存储器的可寻址存储位置接收控制信息，以对所述控制信息进行逻辑运算，并根据所述控制信息生成控制信号（1609）; 用于从所述控制器存储器（1258）接收重复指令信号并用于向所述程序计数器（1584）和所述控制逻辑（1586）发送保持计数信号（1233）的重复计数器（1294），使得所述程序计数器（1584） ）继续选择相同的可寻址存储位置，并且控制逻辑（586）重复发送控制信号（1609）; 以及用于从控制逻辑（1586）接收控制信号的寄存器地址计数器（1290），来自重复计数器（1294）的保持计数信号（1233）和来自控制器存储器的寄存器地址信号（1604）。 存储在寄存器地址计数器（1290）中的寄存器地址信号指向多个寄存器之一。 如果重复计数器（1294）发送保持计数信号，则寄存器地址计数器（1290）接收并存储地址信号，并且如果重复计数器（1294）发送保持，则将寄存器地址信号递增到下一个连续寄存器 计数信号。

    Second nearest-neighbor communication network for synchronous vector processor, systems and methods
    5.
    发明授权
    Second nearest-neighbor communication network for synchronous vector processor, systems and methods 失效
    用于同步向量处理器的第二最近邻通信网络，系统和方法

    公开(公告)号：US5163120A

    公开(公告)日：1992-11-10

    申请号：US421499

    申请日：1989-10-13

    申请人： Jim Childers ,  Peter Reinecke ,  Hiroshi Miyaguchi

    发明人： Jim Childers ,  Peter Reinecke ,  Hiroshi Miyaguchi

    IPC分类号： F02B75/02 ,  G06F15/80

    CPC分类号： G06F15/8015 ,  F02B2075/027

    摘要： A synchronous vector processor SVP device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and is capable of real-time digital processing of video signals. The SVP includes interconnecting circuitry enabling the individual processor elements to retrieve data from and transmit data to their first and second nearest neighbors on either side. At the chip level external connections are provided to enable cascading of several SVP devices.

    摘要翻译： 具有以线性阵列组织的多个一位处理器元件的同步矢量处理器SVP装置。 处理器元件都由序列发生器，状态机或控制电路（控制器）共同控制，以使得能够作为并行处理装置进行操作。 每个处理器元件包括一组输入寄存器，两组寄存器文件，一组工作寄存器，包括一位全加器/减法器的算术逻辑单元和一组输出寄存器。 在视频应用中，每个处理器元件在水平扫描线的一个像素上操作，并且能够对视频信号进行实时数字处理。 SVP包括互连电路，使得各个处理器元件能够从两侧检索数据并向其第一和第二最近邻居发送数据。 在芯片级别，提供外部连接以实现若干SVP设备的级联。

    Electronic device, method and system for half duplex data transmission
    7.
    发明授权
    Electronic device, method and system for half duplex data transmission 有权
    用于半双工数据传输的电子设备，方法和系统

    公开(公告)号：US09179492B2

    公开(公告)日：2015-11-03

    申请号：US13282076

    申请日：2011-10-26

    申请人： Herbert Meier ,  Andreas Hagl ,  Jim Childers

    发明人： Herbert Meier ,  Andreas Hagl ,  Jim Childers

    IPC分类号： G05B19/00 ,  H04W80/00 ,  B60R25/24 ,  G06K19/07 ,  G06K19/077 ,  G07C9/00

    CPC分类号： H04L5/16 ,  B60R25/24 ,  G06K7/10366 ,  G06K19/0724 ,  G06K19/0726 ,  G06K19/07792 ,  G07C9/00309 ,  G07C2009/00198 ,  H04L5/143 ,  H04L27/12 ,  H04W80/00

    摘要： An electronic device and method for half duplex data transmission in a long range keyless entry and go system, and more specifically to an RFID transponder, a corresponding read/write (R/W) unit and methods for operating the RFID transponder and the R/W-unit. There is a first coil, a second coil and a third coil, being arranged as a three-dimensional antenna, a first capacitor, a second capacitor and a third capacitor couplable in parallel to the first coil, the second coil and the third coil, respectively, for selectively forming a first, a second and a third parallel-resonant circuit for receiving radio signals, a series-resonant circuit for transmitting radio signals and a control stage configured to either use one of the first, second or third parallel-resonant circuits for receiving radio signals or the series-resonant circuit for transmitting signals.

    摘要翻译： 一种用于远程无钥匙进入和离开系统中的半双工数据传输的电子设备和方法，更具体地涉及RFID应答器，相应的读/写（R / W）单元和用于操作RFID​​应答器和R / W单位。 布置有三维天线的第一线圈，第二线圈和第三线圈，与第一线圈，第二线圈和第三线圈并联连接的第一电容器，第二电容器和第三电容器， 分别用于选择性地形成用于接收无线电信号的第一和第二并联谐振电路，用于发送无线电信号的串联谐振电路和被配置为使用第一，第二或第三并联谐振 用于接收无线电信号的电路或用于发送信号的串联谐振电路。

    Distribution of global variables in synchronous vector processor
    8.
    发明授权
    Distribution of global variables in synchronous vector processor 失效
    全局变量在同步向量处理器中的分布

    公开(公告)号：US5293637A

    公开(公告)日：1994-03-08

    申请号：US76277

    申请日：1993-06-10

    申请人： Jim Childers ,  Hiroshi Miyaguchi

    发明人： Jim Childers ,  Hiroshi Miyaguchi

    IPC分类号： F02B75/02 ,  G06F15/80 ,  G06T1/20 ,  G06F15/64

    CPC分类号： G06F15/8007 ,  G06T1/20 ,  F02B2075/027

    摘要： A synchronous vector processor SVP device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and the SVP is capable of real-time digital processing of video signals. In video applications a data input control circuit including a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit is provided. In order to distribute variables to each processor element simultaneously the data input control circuit is provided with a set of auxiliary registers and an addressing structure to modulate one of the processor elements' working registers. In this manner variables are provided to the SVP device in lieu of a designated control instruction bit.

    摘要翻译： 具有以线性阵列组织的多个一位处理器元件的同步矢量处理器SVP装置。 处理器元件都由序列发生器，状态机或控制电路（控制器）共同控制，以使得能够作为并行处理装置进行操作。 每个处理器元件包括一组输入寄存器，两组寄存器文件，一组工作寄存器，包括一位全加器/减法器的算术逻辑单元和一组输出寄存器。 在视频应用中，每个处理器元件在水平扫描线的一个像素上操作，并且SVP能够对视频信号进行实时数字处理。 在视频应用中，提供了包括主控制器电路，垂直定时发生器电路，恒定发电机电路，水平定时发生器电路和指令发生器电路的数据输入控制电路。 为了同时将变量分配给每个处理器元件，数据输入控制电路设置有一组辅助寄存器和寻址结构，以调制处理器元件的工作寄存器之一。 以这种方式，将变量提供给SVP设备来代替指定的控制指令位。

    Redundancy scheme for eliminating defects in a memory device
    9.
    发明授权
    Redundancy scheme for eliminating defects in a memory device 失效
    用于消除存储器件中的缺陷的冗余方案

    公开(公告)号：US5126973A

    公开(公告)日：1992-06-30

    申请号：US479510

    申请日：1990-02-14

    申请人： James D. Gallia ,  Jim Childers

    发明人： James D. Gallia ,  Jim Childers

    IPC分类号： G11C29/00

    CPC分类号： G11C29/808

    摘要： A redundancy scheme for a memory device, as well as a method for developing a redundancy scheme, resulting in improved repairability for given space constraints. A memory device is formed with a plurality of data blocks having individual input/output paths. Each block comprises an array of memory cells arranged in addressable rows and columns along row lines and column lines. The array is configured in sub-blocks each comprising a plurality of the memory cells. The device includes row address circuitry for selecting a row of the memory cells, column address circuitry for selecting a column of the memory cells and address repair circuitry. The address repair circuitry is configurable to render a first portion of a first of the columns of cells responsive to the address of a portion of a second of the columns of cells. There is also provided a method for eliminating a defect in a memory device having a logical data block formed with addressable rows and columns of memory cells. A defect associated with a first column of cells is eliminated by programming a portion of a second column of cells to be responsive to the addresses of a portion of the cells in the first column.