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1.发明授权Low cost digital-to-analog converter with high precision feedback resistor and output amplifier 失效具有高精度反馈电阻和输出放大器的低成本数模转换器
公开(公告)号：US4647906A
公开(公告)日：1987-03-03
申请号：US750338
申请日：1985-06-28
摘要： An integrated circuit digital-to-analog converter includes a nichrome feedback resistor having .+-.1% accuracy in its output amplifier, a plurality of bit current determining resistors that have .+-.30% manufacturing accuracy, a bias voltage circuit that produces a temperature-compensated bias voltage including an integrated potentiometer that is laser trimmed to compensate for the inaccuracy of the bit current determining resistors. The bit current determining resistors thereby produce constant, precise temperature-independent bit currents. The integrated potentiometer is accurately laser trimmed without changing the series resistance of the potentiometer. This prevents current density changes that change the temperature sensitivity of temperature-compensating elements in the bias voltage circuit.
摘要翻译： 集成电路数模转换器包括在其输出放大器中具有+/- 1％精度的镍铬反馈电阻器，具有+/- 30％制造精度的多个位电流确定电阻器，产生 温度补偿偏置电压包括一个集成电位器，该电位器被激光修整以补偿位电流确定电阻器的不准确性。 因此，位电流确定电阻器产生恒定的，精确的与温度无关的位电流。 集成电位器在不改变电位器的串联电阻的情况下精确地进行激光修整。 这可以防止改变偏压电路中的温度补偿元件的温度敏感度的电流密度变化。
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公开(公告)号：US4611178A
公开(公告)日：1986-09-09
申请号：US732168
申请日：1985-05-08
申请人： Jimmy R. Naylor , David F. Mietus
发明人： Jimmy R. Naylor , David F. Mietus
CPC分类号： H03F3/3096
摘要： A low voltage sixteen bit digital-to-analog converter operable between +5 and -5 volt power supplies and capable of providing output voltage levels to within about 1.4 volts of +V.sub.CC and -V.sub.CC includes a push-pull output stage with only a pullup transistor and a pulldown transistor connected in series between the positive and negative supply voltages. The output stage includes circuitry that reduces the base voltage of the pullup transistor or pulldown transistor enough to reduce its collector current to near zero, greatly increasing its effective collector-to-emitter breakdown voltage.
摘要翻译： 一个低电压十六位数模转换器可在+5和-5伏特电源之间工作，能够将输出电压电平提供到+ VCC左右的1.4伏，-VCC包括一个只有上拉电阻的推挽输出级 晶体管和串联连接在正电源电压和负电源电压之间的下拉晶体管。 输出级包括减小上拉晶体管或下拉式晶体管的基极电压的电路，足以将其集电极电流降至接近零，大大增加其有效的集电极 - 发射极击穿电压。
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3.发明授权Digital-to-analog converter having open-loop voltage reference for regulating bit switch currents 失效具有用于调节位开关电流的开环参考电压的数模转换器
公开(公告)号：US4381497A
公开(公告)日：1983-04-26
申请号：US250858
申请日：1981-04-03
摘要： An open-loop voltage reference circuit, adapted to regulate a plurality of bit switch currents within a digital-to-analog converter, includes a zener diode reference leg for developing a reference voltage. The reference leg also includes a base-emitter junction voltage multiplier for creating a compensating voltage having a temperature tracking coefficient that is equal and opposite to that of the zener diode junction voltage. The reference voltage developed by the reference leg is used to bias a temperature independent current within a slave leg, and a current mirror circuit mirrors the current within the slave leg for supplying a constant current to the reference leg. The magnitude of the reference voltage is reduced through a divider leg, and an emitter follower leg provides a low impedance bias voltage for driving the plurality of bit switch current sources. The open-loop voltage reference circuit is further adapted to compensate for second order errors caused by temperature induced variations in current gain and Early effect variations related to changes in the power supply voltage. A Gain Adjust feature is also provided for adjusting the bit switch currents without adversely affecting the regulation thereof.
摘要翻译： 适于调节数模转换器内的多个位开关电流的开环参考电路包括用于开发参考电压的齐纳二极管参考支路。 参考支路还包括基极 - 发射极结电压倍增器，用于产生具有与齐纳二极管结电压相同和相反的温度跟踪系数的补偿电压。 由参考支路产生的参考电压用于偏置从动支路内的独立于温度的电流，并且电流镜电路反映从动支路内的电流，以向参考支路提供恒定电流。 参考电压的幅度通过分路器脚减小，并且射极跟随器腿提供用于驱动多个位开关电流源的低阻抗偏置电压。 开环电压参考电路还适于补偿由温度引起的电流增益变化和与电源电压变化相关的早期效应变化引起的二阶误差。 还提供增益调整功能，用于调整位开关电流，而不会对其调节产生不利影响。
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4.发明授权Dual analog-to-digital converter with single successive approximation register 失效具有单个逐次逼近寄存器的双模数转换器
公开(公告)号：US4940981A
公开(公告)日：1990-07-10
申请号：US308150
申请日：1989-02-08
申请人： Jimmy R. Naylor , Rodney T. Burt , Tony D. Miller
发明人： Jimmy R. Naylor , Rodney T. Burt , Tony D. Miller
CPC分类号： H03M1/0607 , H03F3/45188 , H03K5/2481 , H03M1/123 , H03F2203/45456 , H03F2203/45462 , H03F2203/45508 , H03F2203/45652 , H03F2203/45702 , H03M1/468
摘要： A dual successive approximation analog-to-digital converter, including circuitry for generating separate reference voltages for each analog-to-digital converter, is integrated onto a single semiconductor chip. A single successive approximation register including a 19 bit shift register and two 18 bit latches and associated gating circuitry operates to produce two sets of 18 successive approximation numbers, one supplied as successive digital inputs to a CDAC of one of the analog-to-digital converters and the other set of successive approximation numbers being applied as digital inputs to a CDAC of the other analog-to-digital converter. A CMOS comparator includes two high speed, low gain differential amplifier stages, the first including cascode MOSFETs to provide a high power supply rejection. A pair of auto-zeroing capacitors and a pair of auto-zeroing MOSFETs operate on the outputs of the second differential amplifier to reduce input offset voltage, achieving high speed, low noise operation in a small amount of semiconductor chip area. The auto-zeroed output is supplied to the input of a two stage differential amplifier, the outputs of which also are auto-zeroed and applied to a differential CMOS latch, thereby providing a high speed, low noise, low offset CMOS comparator.
摘要翻译： 包括用于为每个模数转换器产生单独参考电压的电路的双逐次逼近模数转换器被集成到单个半导体芯片上。 包括19位移位寄存器和两个18位锁存器和相关门控电路的单个逐次逼近寄存器操作以产生两组18个逐次逼近数字，一组作为连续的数字输入提供给模数转换器之一的CDAC 并且另一组逐次逼近数字被用作数字输入到另一模数转换器的CDAC。 CMOS比较器包括两个高速，低增益差分放大器级，第一个包括共源共栅MOSFET，以提供高电源抑制。 一对自动归零电容器和一对自动归零MOSFET在第二差分放大器的输出上工作，以减少输入失调电压，实现少量半导体芯片面积的高速度，低噪声运行。 自动归零输出被提供给两级差分放大器的输入，它们的输出也被自动归零并应用于差分CMOS锁存器，从而提供高速，低噪声，低失调的CMOS比较器。
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公开(公告)号：US5969658A
公开(公告)日：1999-10-19
申请号：US972606
申请日：1997-11-18
申请人： Jimmy R. Naylor
发明人： Jimmy R. Naylor
摘要： A digital-to-analog converter includes an input circuit (9) producing a plurality of corresponding switch control signals (25) in response to a digital input signal (D.sub.IN) and a resistive ladder network (10A) including an R/2R MSB ladder section (2) including a plurality of "R" resistors (17) and a plurality of "2R" resistors (5), and an R/2R LSB ladder section (3) including a plurality of "R" resistors (17) and a plurality of "2R" resistors (5). A scaling resistor (21) is coupled between a least significant node conductor (7-3) of the MSB ladder section and a most significant node conductor (7-4) of the LSB ladder section. A plurality of switch circuits (6) each selectively conducts a respective parallel resistor circuit (5) to a first reference voltage conductor (VREFH) or a second reference voltage conductor (VREFL) in response to the various switch control signals (25). The resistances of the resistors of the "R" resistors of the MSB ladder section are different than the resistances of the resistors of the "R" resistors of the LSB ladder section. The resistances of the "R" resistors of the MSB ladder section, the resistances of the "R" resistors of the LSB ladder section, and the resistance of the scaling resistor are related by the expression R"=2R-R', where R" is the resistance of a scaling resistor, R is the resistance of the "R" resistors of the MSB ladder section, and R' is the resistance of the "R" resistors of the LSB ladder section.
摘要翻译： 数模转换器包括响应于数字输入信号（DIN）和包括R / 2R MSB梯形图的电阻梯形网络（10A）产生多个对应的开关控制信号（25）的输入电路（9） 包括多个“R”电阻器（17）和多个“2R”电阻器（5）的部分（2）和包括多个“R”电阻器（17）的R / 2R LSB梯形部分（3） 多个“2R”电阻器（5）。 缩放电阻器（21）耦合在MSB梯形部分的最低有效节点导体（7-3）和LSB梯形部分的最高有效节点导体（7-4）之间。 响应于各种开关控制信号（25），多个开关电路（6）各自选择性地将相应的并联电阻器电路（5）传导到第一参考电压导体（VREFH）或第二参考电压导体（VREFL）。 MSB梯形截面的“R”电阻的电阻的阻值与LSB梯形截面的“R”电阻的电阻不同。 MSB梯形部分的“R”电阻，LSB梯形部分的“R”电阻的电阻和比例电阻的电阻的电阻与表达式R“= 2R-R'相关，其中 R“是缩放电阻的电阻，R是MSB梯形截面的”R“电阻的电阻，R'是LSB梯形截面的”R“电阻的电阻。
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6.发明授权
公开(公告)号：US06150971A
公开(公告)日：2000-11-21
申请号：US337796
申请日：1999-06-22
IPC分类号： H03M1/78 , H03K17/00 , H03K17/693 , H03M1/08
摘要： A digital-to-analog converter includes a resistive divider network including a plurality of series resistors of resistance R and a plurality of shunt resistors of resistance 2R' and a circuit for switching a shunt resistor of the resistive divider network in the digital-to-analog converter to either of first and second reference voltages. The switching circuit includes a first switch MOSFET coupling the low reference voltage to the shunt resistor, and a second switch MOSFET coupling the shunt resistor to the high reference voltage. First and second switch control circuits adjust the on resistances of the first and second switch MOSFETs to be proportional to the resistances of first and second reference resistors, which have the same temperature coefficient as the resistors of which the divider network is composed. The on resistance of each of the first and second switch MOSFETs is equal to R.sub.ONi, and the resistance 2R' is equal to 2R-R.sub.ONi. The on resistances do not need to be binarily scaled.
摘要翻译： 数模转换器包括电阻分压网络，其包括电阻R的多个串联电阻器和多个电阻2R'的分流电阻器，以及用于在数模转换器中切换电阻分压器网络的分流电阻器的电路， 模拟转换器到第一和第二参考电压中的任一个。 开关电路包括将低参考电压耦合到分流电阻器的第一开关MOSFET和将分流电阻器耦合到高参考电压的第二开关MOSFET。 第一和第二开关控制电路将第一和第二开关MOSFET的导通电阻调节成与第一和第二参考电阻的电阻成比例，第一和第二参考电阻具有与构成分压网络的电阻相同的温度系数。 第一和第二开关MOSFET的导通电阻等于RONi，电阻2R'等于2R-RONi。 导通电阻不需要二进制缩放。
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公开(公告)号：US4222107A
公开(公告)日：1980-09-09
申请号：US5357
申请日：1979-01-22
CPC分类号： H03M1/1071
摘要： A system for automatically calibrating a main digital to analog converter (DAC) includes first and second adjustment DAC's, an offset DAC, a difference amplifier, an analog to digital converter (ADC), a microprocessor, and an analog switch. To calibrate the offset of the main DAC, the microprocessor causes "zeros" to be applied to the digital inputs of the main DAC and the offset DAC. The output of the offset DAC is coupled to an input of the difference amplifier. The microprocessor causes a ground voltage to be applied to the second input of the difference amplifier via the analog switch. The output of the difference amplifier is inputted to the ADC, which produces a first word. The first word is stored by the microprocessor. The analog switch is activated to apply the analog output voltage of the main DAC to the second input of the difference amplifier. The ADC produces a second word which is compared to the first word. The microprocessor computes a first correction word which is transmitted to the first adjustment DAC. The first adjustment DAC produces a corresponding analog signal which is applied to a first correction input of the main DAC, causing the analog output voltage to be adjusted toward the ground voltage. To calibrate the linearity of the main DAC, the microprocessor causes the analog voltage corresponding to the fourth most significant bit to be converted to a third digital word by means of the ADC, and then causes the analog output voltage corresponding to the sum of the less significant bits to be converted to a fourth word by means of the ADC. The difference between the third and fourth words is used by the microprocessor to compute a second correction code. The second correction code is converted to a second analog correction signal by the second DAC, causing the third analog output voltage to differ from the second analog output voltage by an amount corresponding to one least significant bit.
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8.发明授权
公开(公告)号：US5235333A
公开(公告)日：1993-08-10
申请号：US846670
申请日：1992-03-05
申请人： Jimmy R. Naylor , Bernd M. Rundel
发明人： Jimmy R. Naylor , Bernd M. Rundel
摘要： A circuit for preventing analog-to-digital conversion errors due to MOS threshold shifts produced in a comparator during successive approximation testing of MSB and LSB groups of binarily weighted bit capacitors includes a first amplifier that amplifies voltage changes produced on a charge distribution conductor connected to the bit capacitors during successive approximation testing of the bit capacitors of the MSB group. The output of the first amplifier subjects a MOSFET in an input stage of the comparator to sufficiently large gate-to-source voltages to produce an MOS threshold shift in the MOSFET. During successive approximation testing of bit capacitors of the LSB group, a second amplifier amplifies signals representative of voltage changes produced on the charge distribution conductor and applies the amplified signals to the same MOSFET. The second amplifier has a sufficiently large gain that the earlier induced MOS threshold shift, when referred back to an input of the amplifier by dividing the MOS threshold shift by the gain, is small enough compared to the voltage changes produced on the charge distribution conductor during the successive approximation testing of the bit capacitors of the LSB group to avoid conversion errors.
摘要翻译： 用于在MSB和二进制加权位电容的LSB组的逐次逼近测试期间防止在比较器中产生的MOS阈值偏移的模数转换误差的电路包括：第一放大器，其放大与连接到 在MSB组的位电容器的逐次近似测试期间的位电容器。 第一放大器的输出使比较器的输入级中的MOSFET达到足够大的栅极至源极电压，以在MOSFET中产生MOS阈值漂移。 在LSB组的位电容器的逐次近似测试期间，第二放大器放大表示在电荷分布导体上产生的电压变化的信号，并将放大的信号施加到同一MOSFET。 第二放大器具有足够大的增益，而较早的感应MOS阈值偏移通过将MOS阈值偏移除以增益而被称为放大器的输入，与电荷分布导体上产生的电压变化相比足够小 对LSB组的位电容进行逐次逼近测试，以避免转换误差。
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公开(公告)号：US4567463A
公开(公告)日：1986-01-28
申请号：US351542
申请日：1982-02-23
申请人： Jimmy R. Naylor
发明人： Jimmy R. Naylor
CPC分类号： H03M1/68
摘要： In a digital to analog converter, a circuit for improving the performance of digital to analog converters by reducing and minimizing the variation in analog ground current is disclosed. The resulting digital to analog converter has reduced variation in output signal, the digital to analog converter can provide a more accurate representation of the input digital signal.
摘要翻译： 在数模转换器中，公开了一种通过减少和最小化模拟地电流的变化来改善数模转换器的性能的电路。 所得到的数模转换器减少了输出信号的变化，数模转换器可以提供输入数字信号的更准确的表示。
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10.发明授权
公开(公告)号：US4423409A
公开(公告)日：1983-12-27
申请号：US250868
申请日：1981-04-03
摘要： A digital-to-analog converter circuit includes an open-loop reference circuit for regulating a plurality of bit switch currents and utilizes a high-speed single-ended input interface network for level shifting digital input signals to the bit switches whereat the level shifted input signals switch against a substantially fixed threshold voltage. The single-ended input interface network includes a PNP input transistor coupled to an input terminal and coupled by a resistor to a regulated voltage. The PNP input transistor is coupled to a level shifting network including an emitter follower transistor and a zener junction biased by a current source. The threshold voltage is also developed by a level shifting network that includes a zener junction for compensating variations within the level shifting network of the single-ended input interface network.
摘要翻译： 数模转换器电路包括用于调节多个位开关电流的开环参考电路，并且利用高速单端输入接口网络将数字输入信号电平移位到位开关，其中电平转换输入 信号切换基本固定的阈值电压。 单端输入接口网络包括耦合到输入端并由电阻器耦合到调节电压的PNP输入晶体管。 PNP输入晶体管耦合到包括射极跟随器晶体管和由电流源偏置的齐纳结的电平移动网络。 门限电压也由包括用于补偿单端输入接口网络的电平转换网络内的变化的齐纳结的电平转换网络开发。
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