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公开(公告)号：US4611178A
公开(公告)日：1986-09-09
申请号：US732168
申请日：1985-05-08
申请人： Jimmy R. Naylor , David F. Mietus
发明人： Jimmy R. Naylor , David F. Mietus
CPC分类号： H03F3/3096
摘要： A low voltage sixteen bit digital-to-analog converter operable between +5 and -5 volt power supplies and capable of providing output voltage levels to within about 1.4 volts of +V.sub.CC and -V.sub.CC includes a push-pull output stage with only a pullup transistor and a pulldown transistor connected in series between the positive and negative supply voltages. The output stage includes circuitry that reduces the base voltage of the pullup transistor or pulldown transistor enough to reduce its collector current to near zero, greatly increasing its effective collector-to-emitter breakdown voltage.
摘要翻译： 一个低电压十六位数模转换器可在+5和-5伏特电源之间工作，能够将输出电压电平提供到+ VCC左右的1.4伏，-VCC包括一个只有上拉电阻的推挽输出级 晶体管和串联连接在正电源电压和负电源电压之间的下拉晶体管。 输出级包括减小上拉晶体管或下拉式晶体管的基极电压的电路，足以将其集电极电流降至接近零，大大增加其有效的集电极 - 发射极击穿电压。
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2.发明授权Low cost digital-to-analog converter with high precision feedback resistor and output amplifier 失效具有高精度反馈电阻和输出放大器的低成本数模转换器
公开(公告)号：US4647906A
公开(公告)日：1987-03-03
申请号：US750338
申请日：1985-06-28
摘要： An integrated circuit digital-to-analog converter includes a nichrome feedback resistor having .+-.1% accuracy in its output amplifier, a plurality of bit current determining resistors that have .+-.30% manufacturing accuracy, a bias voltage circuit that produces a temperature-compensated bias voltage including an integrated potentiometer that is laser trimmed to compensate for the inaccuracy of the bit current determining resistors. The bit current determining resistors thereby produce constant, precise temperature-independent bit currents. The integrated potentiometer is accurately laser trimmed without changing the series resistance of the potentiometer. This prevents current density changes that change the temperature sensitivity of temperature-compensating elements in the bias voltage circuit.
摘要翻译： 集成电路数模转换器包括在其输出放大器中具有+/- 1％精度的镍铬反馈电阻器，具有+/- 30％制造精度的多个位电流确定电阻器，产生 温度补偿偏置电压包括一个集成电位器，该电位器被激光修整以补偿位电流确定电阻器的不准确性。 因此，位电流确定电阻器产生恒定的，精确的与温度无关的位电流。 集成电位器在不改变电位器的串联电阻的情况下精确地进行激光修整。 这可以防止改变偏压电路中的温度补偿元件的温度敏感度的电流密度变化。
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公开(公告)号：US5337606A
公开(公告)日：1994-08-16
申请号：US926616
申请日：1992-08-10
申请人： Paul T. Bennett , Ronald J. Gutteridge , Daniel N. Koury, Jr. , David F. Mietus , Ljubisa Ristic
发明人： Paul T. Bennett , Ronald J. Gutteridge , Daniel N. Koury, Jr. , David F. Mietus , Ljubisa Ristic
IPC分类号： G01P15/08 , G01P15/125 , H01L29/84 , H01G7/00
CPC分类号： G01P15/125 , G01P15/0802 , Y10T29/43
摘要： A micromachined capacitor structure having a first anchor (12) attached to the substrate (24), a tether (13) coupled to the anchor (12) and having a portion free to move in a lateral direction over the substrate (24) in response to acceleration. A tie-bar (14) is coupled to the movable portion of the tether (13), and at least one movable capacitor plate (16) is coupled to the tie bar (13). A first fixed capacitor plate (16) is attached to the substrate (24) laterally overlapping and vertically spaced from the at least one movable capacitor plate (16).
摘要翻译： 一种微加工电容器结构，其具有附接到所述基板（24）的第一锚固件（12），联接到所述锚固件（12）的系绳（13），并且具有在所述基板（24）上沿横向移动的部分，以响应 加速。 连杆（14）联接到系绳（13）的可移动部分，并且至少一个可移动电容器板（16）联接到连接杆（13）。 第一固定电容器板（16）与至少一个可移动电容器板（16）横向重叠并垂直间隔地安装到基板（24）。
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公开(公告)号：US07012378B1
公开(公告)日：2006-03-14
申请号：US10773962
申请日：2004-02-06
申请人： Michael A. Wells , David F. Mietus
发明人： Michael A. Wells , David F. Mietus
IPC分类号： G05F1/00
CPC分类号： G09G3/32 , G09G2300/0809 , G09G2310/0272
摘要： A programmable multiple current source includes a plurality of current source circuits each having current level data storage circuitry. A current level data input terminal and a control input terminal are connected to each current source circuit to supply current level data to the storage circuitry. Peak detector and storage circuitry is coupled to each of the output terminals of the current source circuits. Each associated current source circuit includes a master digital-to-analog converter coupled to the current level data storage circuitry, a driver circuit coupled to the digital-to-analog converter and to the associated current source circuit, comparator and storage circuitry having a first input coupled to the peak detector and storage circuitry and a second input coupled to the driver circuit, and current level adjustment circuitry coupled to the comparator and storage circuitry and the driver circuit.
摘要翻译： 可编程多电流源包括多个电流源电路，每个电流源电路具有电流数据存储电路。 电流电平数据输入端子和控制输入端子连接到每个电流源电路以将电流电平数据提供给存储电路。 峰值检测器和存储电路耦合到电流源电路的每个输出端子。 每个相关联的电流源电路包括耦合到当前电平数据存储电路的主数模转换器，耦合到数 - 模转换器的驱动电路和相关联的电流源电路，比较器和存储电路，其具有第一 耦合到峰值检测器和存储电路的输入和耦合到驱动器电路的第二输入以及耦合到比较器和存储电路和驱动器电路的电流电平调整电路。
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5.发明授权Input/output electrostatic discharge protection circuit for an integrated circuit 失效用于集成电路的输入/输出静电放电保护电路
公开(公告)号：US5610425A
公开(公告)日：1997-03-11
申请号：US384047
申请日：1995-02-06
申请人： John H. Quigley , David F. Mietus
发明人： John H. Quigley , David F. Mietus
IPC分类号： H01L29/74 , H01L21/822 , H01L27/02 , H01L27/04 , H01L29/749 , H01L29/866 , H02H7/20 , H05F3/02 , H01L23/62
CPC分类号： H01L27/0262 , H01L27/0251 , H01L2924/0002
摘要： An Input/Output (I/O) circuit (11) for an integrated circuit including Electrostatic Discharge Protection (ESD) circuitry is disclosed. A Silicon Controlled Rectifier SCR (30) is triggered by a transistor (36) which is scaled to an output transistor (24) of the I/O circuit (11) to shunt an ESD event. The SCR (30) couples between a pad (12) and a power supply line V.sub.SS. The transistor (36) is disabled. The triggering mechanism is voltage breakdown of the transistor (36) due to an ESD event. The SCR protection mechanism is process independent since the triggering mechanism is formed similarly to the output transistor (24) and thus breaks-down similarly. Zener diodes (26-29) are coupled to gates of the I/O circuit (11) and between the power supply lines. A phosphorous doping less than 5.0 E18 per cubic centimeter is used to form the cathode of zener diodes (26-29).
摘要翻译： 公开了一种用于包括静电放电保护（ESD）电路的集成电路的输入/输出（I / O）电路（11）。 硅控整流器SCR（30）由晶体管（36）触发，晶体管（36）被缩放到I / O电路（11）的输出晶体管（24）以分流ESD事件。 SCR（30）耦合在焊盘（12）和电源线VSS之间。 晶体管（36）被禁止。 触发机制是由于ESD事件引起的晶体管（36）的电压击穿。 SCR保护机制是独立于过程的，因为触发机制类似于输出晶体管（24）形成并因此类似地分解。 齐纳二极管（26-29）耦合到I / O电路（11）的栅极和电源线之间。 使用小于5.0E18 /立方厘米的磷掺杂形成齐纳二极管（26-29）的阴极。
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公开(公告)号：US5198701A
公开(公告)日：1993-03-30
申请号：US632793
申请日：1990-12-24
摘要： A current source with adjustable temperature compensation in which the level of current supplied to a load is adjusted to compensate for the load's inherent change in performance with changes in temperature. The current source allows selection of the appropriate temperature compensating characteristic and operating current solely by altering internal component values.
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7.发明授权
公开(公告)号：US6041221A
公开(公告)日：2000-03-21
申请号：US859898
申请日：1997-05-21
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A memory circuit (24) limits the threshold voltage distribution for either programming or erasing a memory cell (40A) in a non-volatile memory array (34). A data latch (90) provides a current (I.sub.REF) to the memory cell (40A) that increases in current as the operating temperature of the memory cells (40A, 40B) increases. Current generated by the data latch (90) increases when the processing parameters cause a greater conductivity of the transistors in the memory cell (40A) and the current decreases when the processing parameters cause a lesser conductivity of the transistors in the memory cell (40A), thus allowing narrower limits on the distribution of the program and erase threshold voltages.
摘要翻译： 存储器电路（24）限制用于编程或擦除非易失性存储器阵列（34）中的存储器单元（40A）的阈值电压分布。 当存储器单元（40A，40B）的工作温度升高时，数据锁存器（90）向存储器单元（40A）提供电流（IREF），其随着电流的增加而增加。 当处理参数导致存储单元（40A）中的晶体管的较大导电性并且当处理参数导致存储单元（40A）中的晶体管的较小导电性时，电流减小，由数据锁存器（90）产生的电流增加， ，从而允许对编程分布的较窄限制和擦除阈值电压。
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公开(公告)号：US5898617A
公开(公告)日：1999-04-27
申请号：US859962
申请日：1997-05-21
CPC分类号： G11C16/28
摘要： A circuit (28) and method of sensing data stored in a memory circuit provide a reference current (I.sub.REF) that tracks memory cell current (I.sub.BIT) over a range of temperatures and power supply voltages. A comparator circuit (66) senses the memory cell current with respect to the reference current to produce the stored data (V.sub.DATA) By sensing current rather than voltage, the voltage swing on a high capacitance bitline (39) can be reduced to improve speed. The reference current is set during testing of the circuit by applying programming voltages (V.sub.WELL, V.sub.CG, V.sub.BL) to a reference device (52) that matches a storage device (36) in the memory cell (30).
摘要翻译： 检测存储在存储器电路中的数据的电路（28）和方法提供在温度范围和电源电压上跟踪存储单元电流（IBIT）的参考电流（IREF）。 比较器电路（66）相对于参考电流感测存储单元电流以产生存储的数据（VDATA）通过感测电流而不是电压，可以减小高电容位线（39）上的电压摆幅以提高速度。 通过将编程电压（VWELL，VCG，VBL）应用于与存储单元（30）中的存储装置（36）匹配的参考装置（52），在电路测试期间设置参考电流。
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公开(公告)号：US5754010A
公开(公告)日：1998-05-19
申请号：US859963
申请日：1997-05-21
摘要： A memory circuit (24) includes a sense amp circuit (30) that uses multiplexers (86) in a column mux (32) for pre-charging only selected bitlines in order to limit the current during a read operation of the FLASH memory circuit (24). The sense amp circuit (30) provides the bitline with a pre-charge voltage that is set by a current reference (68) that is substantially supply independent. In the read mode the sense amp circuit (30) responds to either a voltage on the bitline that is lowered from the pre-charge voltage value by a selected programmed memory cell (40) or by a voltage that remains at the pre-charged voltage value for an unprogrammed memory cell.
摘要翻译： 存储器电路（24）包括读出放大器电路（30），该读出放大器电路使用列复用器（32）中的多路复用器（86）来仅预选所选择的位线，以便在闪速存储器电路的读取操作期间限制电流 24）。 感测放大器电路（30）为位线提供由基本上独立供电的电流基准（68）设置的预充电电压。 在读取模式下，感测放大器电路（30）响应来自预充电电压值的位线上的电压由选择的编程存储器单元（40）或保持在预充电电压 未编程存储单元的值。
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10.发明授权
公开(公告)号：US5418674A
公开(公告)日：1995-05-23
申请号：US95573
申请日：1993-07-19
申请人： Robert B. Davies , David F. Mietus
发明人： Robert B. Davies , David F. Mietus
IPC分类号： H03K17/042 , H03K17/08 , H03K17/0812 , H03K17/082 , H03K17/16 , H03K17/18 , H03K17/30 , H02H9/00
CPC分类号： H03K17/04213 , H03K17/08126 , H03K17/0826 , H03K17/16 , H03K17/18 , H03K17/30 , H03K2017/0806
摘要： A multi-leaded protected power device having a boot-strap input has been provided. The power device includes a current controlled, boot-strap driven control die (20) for use with a power transistor (25). The control die includes an under voltage lock-out circuit (46) which inhibits drive to the power transistor until the input signals exceed a predetermined threshold level. Moreover, the control die includes a noise immunity enhancement circuit (56) for providing an excess reverse bias across an output SCR (58) for preventing false triggering of the output SCR. The power device further includes a status output lead (204) for indicating when a voltage occurring across the power transistor has exceeded a predetermined threshold, and a current output lead (220) for providing a current that is proportional to a current flowing through the power transistor.
摘要翻译： 已经提供了具有引导输入的多引线受保护的功率器件。 功率器件包括用于与功率晶体管（25）一起使用的电流控制的引导带驱动的控制管芯（20）。 控制管芯包括欠压锁定电路（46），其阻止对功率晶体管的驱动，直到输入信号超过预定阈值电平。 此外，控制管芯包括用于在输出SCR（58）上提供过大的反向偏置以防止输出SCR的错误触发的抗噪声增强电路（56）。 所述功率器件还包括状态输出引线（204），用于指示所述功率晶体管两端出现的电压何时已经超过预定阈值;以及电流输出引线（220），用于提供与流过所述功率的电流成比例的电流 晶体管。
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