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公开(公告)号：US20120097840A1
公开(公告)日：2012-04-26
申请号：US13276927
申请日：2011-10-19
申请人： Jin Woo Kim , Seog Heon Ham , Kyung-Min Kim , Yong Lim
发明人： Jin Woo Kim , Seog Heon Ham , Kyung-Min Kim , Yong Lim
IPC分类号： H03M1/34 , H01L27/146 , H03M1/12
CPC分类号： H03M1/002 , H03M1/123 , H03M1/56 , H04N5/37213 , H04N5/378
摘要： An analog-to-digital converter (ADC) within an image sensor includes a comparator comparing a ramp signal with an image signal, and a counter generating a count result in response to the comparison by counting a clock during a counting interval. The ADC determines whether a first counting interval for the counter is less than a reference interval, and if the first counting interval is less than the reference interval the counting interval is a first counting interval, else the counting interval is a second counting interval.
摘要翻译： 图像传感器内的模数转换器（ADC）包括将斜坡信号与图像信号进行比较的比较器，以及通过在计数间隔期间对时钟进行计数来产生响应于比较的计数结果的计数器。 ADC确定计数器的第一计数间隔是否小于参考间隔，并且如果第一计数间隔小于参考间隔，则计数间隔是第一计数间隔，否则计数间隔是第二计数间隔。
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2.发明授权Analog-to-digital converter using variable counting interval and image sensor including same 有权使用可变计数间隔的模数转换器和包括其的图像传感器公开(公告)号：US08946616B2
公开(公告)日：2015-02-03
申请号：US13276927
申请日：2011-10-19
申请人： Jin Woo Kim , Seog Heon Ham , Kyung-Min Kim , Yong Lim
发明人： Jin Woo Kim , Seog Heon Ham , Kyung-Min Kim , Yong Lim
CPC分类号： H03M1/002 , H03M1/123 , H03M1/56 , H04N5/37213 , H04N5/378
摘要： An analog-to-digital converter (ADC) within an image sensor includes a comparator comparing a ramp signal with an image signal, and a counter generating a count result in response to the comparison by counting a clock during a counting interval. The ADC determines whether a first counting interval for the counter is less than a reference interval, and if the first counting interval is less than the reference interval the counting interval is a first counting interval, else the counting interval is a second counting interval.
摘要翻译： 图像传感器内的模数转换器（ADC）包括将斜坡信号与图像信号进行比较的比较器，以及通过在计数间隔期间对时钟进行计数来产生响应于比较的计数结果的计数器。 ADC确定计数器的第一计数间隔是否小于参考间隔，并且如果第一计数间隔小于参考间隔，则计数间隔是第一计数间隔，否则计数间隔是第二计数间隔。
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3.发明授权Image data processing method, image sensor and image data processing system using the method 有权图像数据处理方法，图像传感器和图像数据处理系统采用该方法公开(公告)号：US08681251B2
公开(公告)日：2014-03-25
申请号：US13154537
申请日：2011-06-07
申请人： Jin-Woo Kim , Kyung-Min Kim
发明人： Jin-Woo Kim , Kyung-Min Kim
CPC分类号： H04N5/374 , H04N5/23245 , H04N5/3456 , H04N5/376
摘要： An image sensor supporting a normal sampling mode and a 1/N sampling mode for transmitting image data detected by a plurality of unit image sensors and stored in a plurality of latch circuits to a data processor using a plurality of transmission lines, wherein N is a natural number greater than 2, the image sensor including a horizontal address generator configured to generate horizontal addresses corresponding to addresses of the plurality of latch circuits, and to generate, based on the horizontal addresses, a first channel selection control signal and a second channel selection control signal of which activation times at least partially overlap.
摘要翻译： 支持正常采样模式的图像传感器和用于将由多个单位图像传感器检测并被存储在多个锁存电路中的图像数据传送到使用多条传输线路的数据处理器的1 / N采样模式，其中N是 自然数大于2，图像传感器包括水平地址发生器，其被配置为生成对应于多个锁存电路的地址的水平地址，并且基于水平地址生成第一信道选择控制信号和第二信道选择 其激活时间至少部分重叠的控制信号。
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4.发明申请ANALOG-TO-DIGITAL CONVERTER, IMAGE SENSOR INCLUDING THE SAME AND METHOD OF OPERATING IMAGE SENSOR 有权模拟数字转换器，包括其的图像传感器和操作图像传感器的方法公开(公告)号：US20150188559A1
公开(公告)日：2015-07-02
申请号：US14501476
申请日：2014-09-30
申请人： Kyung-Min Kim , Jin-Woo Kim , Sung-Ho Suh , Hee-Sung Chae
发明人： Kyung-Min Kim , Jin-Woo Kim , Sung-Ho Suh , Hee-Sung Chae
摘要： An image sensor includes a pixel array, a plurality of comparators, a plurality of counters and a plurality of synchronization circuits. The pixel array includes a plurality of pixels configured to generate analog signals by sensing incident light. The comparators generate comparison signals by comparing the analog signals with a reference signal. The counters are grouped into a plurality of counter groups. Each of the counters generates digital signals corresponding to the analog signals by counting, the counting terminated by the comparison signals. Each of the synchronization circuits synchronizes input clock signals to a source clock signal to provide synchronized input clock signals to each of the counter groups.
摘要翻译： 图像传感器包括像素阵列，多个比较器，多个计数器和多个同步电路。 像素阵列包括被配置为通过感测入射光来产生模拟信号的多个像素。 比较器通过将模拟信号与参考信号进行比较来产生比较信号。 计数器被分组成多个计数器组。 每个计数器通过计数产生对应于模拟信号的数字信号，由比较信号终止计数。 每个同步电路将输入时钟信号同步到源时钟信号，以向每个计数器组提供同步的输入时钟信号。
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5.发明申请IMAGE DATA PROCESSING METHOD, IMAGE SENSOR AND IMAGE DATA PROCESSING SYSTEM USING THE METHOD 有权图像数据处理方法，图像传感器和使用该方法的图像数据处理系统公开(公告)号：US20110298957A1
公开(公告)日：2011-12-08
申请号：US13154537
申请日：2011-06-07
申请人： Jin-Woo KIM , Kyung-Min Kim
发明人： Jin-Woo KIM , Kyung-Min Kim
IPC分类号： H04N5/335 , H01L27/146
CPC分类号： H04N5/374 , H04N5/23245 , H04N5/3456 , H04N5/376
摘要： An image sensor supporting a normal sampling mode and a 1/N sampling mode for transmitting image data detected by a plurality of unit image sensors and stored in a plurality of latch circuits to a data processor using a plurality of transmission lines, wherein N is a natural number greater than 2, the image sensor including a horizontal address generator configured to generate horizontal addresses corresponding to addresses of the plurality of latch circuits, and to generate, based on the horizontal addresses, a first channel selection control signal and a second channel selection control signal of which activation times at least partially overlap.
摘要翻译： 支持正常采样模式的图像传感器和用于将由多个单位图像传感器检测并被存储在多个锁存电路中的图像数据传送到使用多条传输线路的数据处理器的1 / N采样模式，其中N是 自然数大于2，图像传感器包括水平地址发生器，其被配置为生成与多个锁存电路的地址相对应的水平地址，并且基于水平地址生成第一信道选择控制信号和第二信道选择 其激活时间至少部分重叠的控制信号。
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6.发明申请DOUBLE DATA RATE (DDR) COUNTER, ANALOG-TO-DIGITAL CONVERTER (ADC) USING THE SAME, CMOS IMAGE SENSOR USING THE SAME AND METHODS IN DDR COUNTER, ADC AND CMOS IMAGE SENSOR 有权使用相同数据速率（DDR）计数器，模数转换器（ADC），使用相同的CMOS图像传感器和DDR计数器，ADC和CMOS图像传感器中的方法公开(公告)号：US20100225796A1
公开(公告)日：2010-09-09
申请号：US12632168
申请日：2009-12-07
申请人： Yong Lim , Kyoung-Min Koh , Kyung-Min Kim
发明人： Yong Lim , Kyoung-Min Koh , Kyung-Min Kim
CPC分类号： H04N5/378 , H03M1/0607 , H03M1/123 , H03M1/1295 , H03M1/56 , H04N5/3698
摘要： In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The counter includes at least one second stage for generating another bit of the value in the counter. An input clock signal is applied to a data input of the first stage and a clock input of the second stage.
摘要翻译： 在例如CMOS图像传感器和方法中的例如模数转换中使用的双数据速率（DDR）计数器和计数方法中，计数器的第一级产生最低有效位（LSB） ）在柜台的价值。 计数器包括用于在计数器中产生值的另一位的至少一个第二级。 输入时钟信号被施加到第一级的数据输入端和第二级的时钟输入端。
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公开(公告)号：US08115845B2
公开(公告)日：2012-02-14
申请号：US12320624
申请日：2009-01-30
申请人： Kyoung Min Koh , Kyung-Min Kim , Yong Lim
发明人： Kyoung Min Koh , Kyung-Min Kim , Yong Lim
摘要： A counter array and an image sensor including the same may be provided. The counter array may include a controller and a plurality of counter units. The controller may output an operation control signal and a direction indication signal. The counter units hold previous output values or may perform a counting operation in response to the operation control signal and may perform an up-count operation or a down-count operation in response to the direction indication signal when performing the counting operation.
摘要翻译： 可以提供一种计数器阵列和包括该计数器阵列的图像传感器。 计数器阵列可以包括控制器和多个计数器单元。 控制器可以输出操作控制信号和方向指示信号。 计数器单元保持以前的输出值，或者可以响应于操作控制信号执行计数操作，并且可以在执行计数操作时响应于方向指示信号执行向上计数操作或递减计数操作。
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8.发明授权Double data rate (DDR) counter, analog-to-digital converter (ADC) using the same, CMOS image sensor using the same and methods in DDR counter, ADC and CMOS image sensor 有权双数据速率（DDR）计数器，使用相同的模数转换器（ADC），使用相同的CMOS图像传感器和DDR计数器，ADC和CMOS图像传感器公开(公告)号：US08395539B2
公开(公告)日：2013-03-12
申请号：US12632168
申请日：2009-12-07
申请人： Yong Lim , Kyoung-Min Koh , Kyung-Min Kim
发明人： Yong Lim , Kyoung-Min Koh , Kyung-Min Kim
IPC分类号： H03M1/56
CPC分类号： H04N5/378 , H03M1/0607 , H03M1/123 , H03M1/1295 , H03M1/56 , H04N5/3698
摘要： In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The counter includes at least one second stage for generating another bit of the value in the counter. An input clock signal is applied to a data input of the first stage and a clock input of the second stage.
摘要翻译： 在例如CMOS图像传感器和方法中的例如模数转换中使用的双数据速率（DDR）计数器和计数方法中，计数器的第一级产生最低有效位（LSB） ）在柜台的价值。 计数器包括用于在计数器中产生值的另一位的至少一个第二级。 输入时钟信号被施加到第一级的数据输入端和第二级的时钟输入端。
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9.发明授权Double data rate (DDR) counter, analog-to-digital converter (ADC) using the same, CMOS image sensor using the same and methods in DDR counter, ADC and CMOS image sensor 有权双数据速率（DDR）计数器，使用相同的模数转换器（ADC），使用相同的CMOS图像传感器和DDR计数器，ADC和CMOS图像传感器公开(公告)号：US07990304B2
公开(公告)日：2011-08-02
申请号：US12590830
申请日：2009-11-13
申请人： Yong Lim , Kyoung-Min Koh , Kyung-Min Kim
发明人： Yong Lim , Kyoung-Min Koh , Kyung-Min Kim
IPC分类号： H03M1/34
CPC分类号： H03K21/023 , H03K21/38 , H03K23/548
摘要： In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The first stage includes a first clock input and is edge-triggered on one of the rising and falling edges of a signal applied at the first clock input. The counter includes at least one second stage for generating another bit of the value in the counter. The second stage includes a second clock input and is edge-triggered on the other of the rising and falling edges of a signal applied at the second clock input.
摘要翻译： 在例如CMOS图像传感器和方法中的例如模数转换中使用的双数据速率（DDR）计数器和计数方法中，计数器的第一级产生最低有效位（LSB） ）在柜台的价值。 第一级包括第一时钟输入，并且在第一时钟输入处施加的信号的上升沿和下降沿中的一个边沿触发。 计数器包括用于在计数器中产生值的另一位的至少一个第二级。 第二级包括第二时钟输入，并且在第二时钟输入处施加的信号的上升沿和下降沿中的另一个边沿触发。
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10.发明申请Double data rate (DDR) counter, analog-to-digital converter (ADC) using the same, CMOS image sensor using the same and methods in DDR counter, ADC and CMOS image sensor 有权双数据速率（DDR）计数器，使用相同的模数转换器（ADC），使用相同的CMOS图像传感器和DDR计数器，ADC和CMOS图像传感器公开(公告)号：US20100207798A1
公开(公告)日：2010-08-19
申请号：US12590830
申请日：2009-11-13
申请人： Yong Lim , Kyoung-Min Koh , Kyung-Min Kim
发明人： Yong Lim , Kyoung-Min Koh , Kyung-Min Kim
CPC分类号： H03K21/023 , H03K21/38 , H03K23/548
摘要： In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The first stage includes a first clock input and is edge-triggered on one of the rising and falling edges of a signal applied at the first clock input. The counter includes at least one second stage for generating another bit of the value in the counter. The second stage includes a second clock input and is edge-triggered on the other of the rising and falling edges of a signal applied at the second clock input.
摘要翻译： 在例如CMOS图像传感器和方法中的例如模数转换中使用的双数据速率（DDR）计数器和计数方法中，计数器的第一级产生最低有效位（LSB） ）在柜台的价值。 第一级包括第一时钟输入，并且在第一时钟输入处施加的信号的上升沿和下降沿中的一个边沿触发。 计数器包括用于在计数器中产生值的另一位的至少一个第二级。 第二级包括第二时钟输入，并且在第二时钟输入处施加的信号的上升沿和下降沿中的另一个边沿触发。
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