利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.026 秒)

    Semiconductor device having trench isolation layer and a method of forming the same
    7.
    发明授权
    Semiconductor device having trench isolation layer and a method of forming the same 失效
    具有沟槽隔离层的半导体器件及其形成方法

    公开(公告)号：US06683354B2

    公开(公告)日：2004-01-27

    申请号：US09990740

    申请日：2001-11-16

    申请人： Jin-Hwa Heo ,  Soo-Jin Hong

    发明人： Jin-Hwa Heo ,  Soo-Jin Hong

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224 ,  Y10S438/978

    摘要： A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer. A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800° C.

    摘要翻译： 提供了一种在半导体衬底中具有沟槽隔离层的半导体器件，其中沟槽隔离层包括氮化硅衬垫，氧化硅衬垫; 以及掩埋层，其中所述掩埋层包括用于填充所述沟槽隔离层的下部的第一掩埋层和用于填充所述沟槽隔离层的上部的第二掩埋层。 半导体器件优选地还包括设置在半导体衬底和氮化硅衬垫之间的氧化硅层。 氧化硅层包括在超过约800℃的温度下致密化的热氧化物层。

    Fin-field effect transistors (Fin-FETs) having protection layers
    8.
    发明授权
    Fin-field effect transistors (Fin-FETs) having protection layers 有权
    具有保护层的鳍场效应晶体管（Fin-FET）

    公开(公告)号：US07535061B2

    公开(公告)日：2009-05-19

    申请号：US11586225

    申请日：2006-10-25

    申请人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

    发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

    IPC分类号： H01L21/84

    CPC分类号： H01L29/7851 ,  H01L29/66795

    摘要： Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is provided on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is provided in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is provided on the first insulation layer and a second insulation layer is provided on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin.

    摘要翻译： 提供了场效应晶体管（Fin-FET）。 翅片设置在集成电路基板上。 翅片限定集成电路基板上的沟槽。 第一绝缘层设置在沟槽中，使得第一绝缘层的表面在鳍片的暴露翅片侧壁的表面下方凹进。 保护层设置在第一绝缘层上，第二绝缘层设置在沟槽中的保护层上，使得保护层位于第二绝缘层和鳍的侧壁之间。

    Structure of trench isolation and a method of forming the same
    9.
    发明授权
    Structure of trench isolation and a method of forming the same 有权
    沟槽隔离结构及其形成方法

    公开(公告)号：US06756654B2

    公开(公告)日：2004-06-29

    申请号：US10215342

    申请日：2002-08-09

    申请人： Jin-Hwa Heo ,  Soo-Jin Hong

    发明人： Jin-Hwa Heo ,  Soo-Jin Hong

    IPC分类号： H01L2176

    CPC分类号： H01L21/76229

    摘要： The present invention is directed toward a structure and method by which trench isolation for a wide trench and a narrow trench formed in first and second regions of a substrate may be achieved without formation of a void in an isolation layer, a groove exposing an isolation layer, or an electrical bridge between gates in a subsequent process. A lower isolation layer is formed on the substrate in a first and second trench. The lower isolation layer is patterned to fill a lower region of the first trench, and an upper isolation pattern is formed to fill the second trench and a remainder of the first trench. An aspect ratio of first trench is reduced, thereby preventing the occurrence of a void in the upper isolation layer, or a gap between the upper isolation layer and the substrate.

    摘要翻译： 本发明涉及一种结构和方法，通过该结构和方法可以实现在衬底的第一和第二区域中形成的宽沟槽和窄沟槽的沟槽隔离，而不会在隔离层中形成空隙，露出隔离层 ，或在后续过程中门之间的电桥。 在第一和第二沟槽中的衬底上形成下隔离层。 图案化下部隔离层以填充第一沟槽的下部区域，并且形成上部隔离图案以填充第二沟槽和第一沟槽的其余部分。 第一沟槽的纵横比减小，从而防止在上隔离层中发生空隙或上隔离层与基板之间的间隙。

    Semiconductor device having trench isolation layer and a method of forming the same
    10.
    发明授权
    Semiconductor device having trench isolation layer and a method of forming the same 失效
    具有沟槽隔离层的半导体器件及其形成方法

    公开(公告)号：US07351661B2

    公开(公告)日：2008-04-01

    申请号：US10734354

    申请日：2003-12-12

    申请人： Jin-Hwa Heo ,  Soo-Jin Hong

    发明人： Jin-Hwa Heo ,  Soo-Jin Hong

    IPC分类号： H01L21/302

    CPC分类号： H01L21/76224 ,  Y10S438/978

    摘要： A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer. A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800° C.

    摘要翻译： 提供了一种在半导体衬底中具有沟槽隔离层的半导体器件，其中沟槽隔离层包括氮化硅衬垫，氧化硅衬垫; 以及掩埋层，其中所述掩埋层包括用于填充所述沟槽隔离层的下部的第一掩埋层和用于填充所述沟槽隔离层的上部的第二掩埋层。 半导体器件优选地还包括设置在半导体衬底和氮化硅衬垫之间的氧化硅层。 氧化硅层包括在超过约800℃的温度下致密化的热氧化物层。