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48 条记录 (耗时 0.034 秒)

    Multi-nary and logic device
    1.
    发明授权
    Multi-nary and logic device 失效
    多功能和逻辑器件

    公开(公告)号：US5463572A

    公开(公告)日：1995-10-31

    申请号：US357246

    申请日：1994-12-13

    申请人： Jin-Up Kim ,  Sun-Young Kim

    发明人： Jin-Up Kim ,  Sun-Young Kim

    IPC分类号： G06F7/50 ,  G06F7/44 ,  G06F7/49 ,  G06F7/501 ,  H03K19/20 ,  G06F7/00

    CPC分类号： G06F7/49

    摘要： An AND logic operation rule capable of carrying out an AND logic operation between binary digits and an AND logic operation between multi-nary digits is defined and an AND logic device utilizing the AND logic operation is disclosed. The AND logic operator having three multi-nary logic inputs consists of two multi-nary AND logic operators having two inputs, respectively. The multi-nary AND logic operator carries out the function of the prior binary AND logic operation and the function of the binary-multi-nary AND logic operation.

    摘要翻译： 定义能够执行二进制数位之间的AND逻辑运算和多数位之间的AND逻辑运算的AND逻辑运算规则，并且公开了利用AND逻辑运算的AND逻辑器件。 具有三个多逻辑逻辑输入的AND逻辑运算器分别由具有两个输入的两个多参数AND逻辑运算符组成。 多逻辑AND逻辑运算符执行先前的二进制AND逻辑运算和二进制多逻辑和逻辑运算的功能。

    Multi-nary OR logic device
    2.
    发明授权
    Multi-nary OR logic device 失效
    多逻辑或逻辑器件

    公开(公告)号：US5463571A

    公开(公告)日：1995-10-31

    申请号：US357245

    申请日：1994-12-13

    申请人： Jin-Up Kim ,  Sun-Young Kim

    发明人： Jin-Up Kim ,  Sun-Young Kim

    IPC分类号： G06F7/50 ,  G06F7/00 ,  G06F7/44 ,  G06F7/501 ,  H03K19/20

    CPC分类号： G06F7/00

    摘要： An OR logic operation rule capable of carrying out an OR logic operation between binary digits and an OR logic operation between multi-nary digits is defined and an OR logic device in accordance the OR logic operation is disclosed. The OR logic operator having three multi-nary logic inputs consists two multi-nary OR logic operator having two inputs, respectively. The multi-nary OR logic operator carries out the function of the prior binary OR logic operation and the function of the binary multi-nary OR logic operation.

    摘要翻译： 定义能够执行二进制数位之间的或逻辑运算与多数位之间的或逻辑运算的逻辑运算规则，并且公开了根据或逻辑运算的或逻辑装置。 具有三个多逻辑逻辑输入的OR逻辑运算器分别包括两个具有两个输入的多逻辑或逻辑运算符。 多逻辑OR逻辑运算符执行先前的二进制OR逻辑运算和二进制多逻辑或逻辑运算的功能。

    Methods Of Forming Semiconductor Devices
    3.
    发明申请
    Methods Of Forming Semiconductor Devices 有权
    形成半导体器件的方法

    公开(公告)号：US20120164831A1

    公开(公告)日：2012-06-28

    申请号：US13313172

    申请日：2011-12-07

    申请人： Sun-Young Kim ,  Jun-Eui Song ,  Tae-Wan Lim

    发明人： Sun-Young Kim ,  Jun-Eui Song ,  Tae-Wan Lim

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76807 ,  H01L21/76831 ,  H01L27/11521 ,  H01L2221/1031

    摘要： Methods of forming a semiconductor device are provided. The methods may include forming a second insulation pattern on a first insulation pattern. The first insulation pattern may cover a plurality of conductive structures, and may include a hole therein. The second insulation pattern may include a trench therein that is connected with the hole. The methods may also include forming a spacer on sidewalls of the hole and the trench. The methods may further include forming a wiring structure in the hole and the trench.

    摘要翻译： 提供了形成半导体器件的方法。 所述方法可以包括在第一绝缘图案上形成第二绝缘图案。 第一绝缘图案可以覆盖多个导电结构，并且其中可以包括孔。 第二绝缘图案可以包括与孔连接的沟槽。 所述方法还可以包括在孔和沟槽的侧壁上形成间隔物。 该方法还可以包括在孔和沟槽中形成布线结构。

    Gate-contact structure and method for forming the same
    4.
    发明授权
    Gate-contact structure and method for forming the same 失效

    公开(公告)号：US06855978B2

    公开(公告)日：2005-02-15

    申请号：US10299535

    申请日：2002-11-18

    申请人： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

    发明人： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

    IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L29/788

    CPC分类号： H01L21/76897 ,  H01L21/76895

    摘要： A gate-contact structure and a method for forming the same are provided. The structure includes a device isolation layer pattern formed at a semiconductor substrate to define an active region; and a gate electrode and a capping pattern, which are sequentially stacked on the semiconductor substrate across the device isolation layer pattern. The capping pattern includes a first gate contact hole that exposes a top surface of the gate electrode. An interlayer insulation layer pattern including a second gate contact hole is disposed to cover an entire surface of the semiconductor substrate including the gate electrode and the capping pattern. The second gate contact hole penetrates the first gate contact hole to expose the top surface of the gate electrode. A gate contact plug is disposed to be connected to the top surface of the gate electrode through the second gate contact hole. Accordingly, the interlayer insulation layer pattern is intervened between the gate contact plug and a sidewall of the capping pattern.

    Retroviral vectors for gene therapy
    5.
    发明授权
    Retroviral vectors for gene therapy 失效
    用于基因治疗的逆转录病毒载体

    公开(公告)号：US06190907B1

    公开(公告)日：2001-02-20

    申请号：US09077205

    申请日：1998-05-20

    申请人： Sun-Young Kim ,  Seon-Hee Kim ,  Paul D. Robbins

    发明人： Sun-Young Kim ,  Seon-Hee Kim ,  Paul D. Robbins

    IPC分类号： C12N1563

    CPC分类号： C12N15/86 ,  A61K48/00 ,  C12N2740/13043 ,  C12N2830/00 ,  C12N2830/15 ,  C12N2830/50 ,  C12N2830/60 ,  C12N2840/203 ,  C12N2840/206

    摘要： The present invention provides novel, improved retroviral vectors which can be used for gene therapy, more specifically, retroviral vectors which are not only safer, more versatile, and more convenient than any other existing vectors, but they also drive high levels of gene expression and high viral titer. In retroviral vectors of the present invention, gag and env coding sequences are deleted, and all or part of U3 can be readily substituted with heterologous, non-retroviral promoter elements. Furthermore, at least one internal ribosome entry site is employed to express more than one genes, and multicloning sites are placed in an insertion site for cloning of a heterologous promoter or a foreign gene.

    摘要翻译： 本发明提供了可用于基因治疗的新型改良的逆转录病毒载体，更具体地说，逆转录病毒载体不仅比任何其它现有载体更安全，更通用，更方便，而且还驱动高水平的基因表达和 高病毒滴度。 在本发明的逆转录病毒载体中，缺失gag和env编码序列，并且U3的全部或部分可以容易地被异源非逆转录病毒启动子元件取代。 此外，使用至少一个内部核糖体进入位点来表达多于一个的基因，并且将多克隆位点置于用于克隆异源启动子或外源基因的插入位点中。