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    Gate-contact structure and method for forming the same
    1.
    发明授权
    Gate-contact structure and method for forming the same 失效

    公开(公告)号：US06855978B2

    公开(公告)日：2005-02-15

    申请号：US10299535

    申请日：2002-11-18

    申请人： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

    发明人： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

    IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L29/788

    CPC分类号： H01L21/76897 ,  H01L21/76895

    摘要： A gate-contact structure and a method for forming the same are provided. The structure includes a device isolation layer pattern formed at a semiconductor substrate to define an active region; and a gate electrode and a capping pattern, which are sequentially stacked on the semiconductor substrate across the device isolation layer pattern. The capping pattern includes a first gate contact hole that exposes a top surface of the gate electrode. An interlayer insulation layer pattern including a second gate contact hole is disposed to cover an entire surface of the semiconductor substrate including the gate electrode and the capping pattern. The second gate contact hole penetrates the first gate contact hole to expose the top surface of the gate electrode. A gate contact plug is disposed to be connected to the top surface of the gate electrode through the second gate contact hole. Accordingly, the interlayer insulation layer pattern is intervened between the gate contact plug and a sidewall of the capping pattern.

    Gate-contact structure and method for forming the same
    3.
    发明授权
    Gate-contact structure and method for forming the same 失效

    公开(公告)号：US07015087B2

    公开(公告)日：2006-03-21

    申请号：US11029832

    申请日：2005-01-04

    申请人： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

    发明人： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/76897 ,  H01L21/76895

    摘要： A gate-contact structure and a method for forming the same are provided. The structure includes a device isolation layer pattern formed at a semiconductor substrate to define an active region; and a gate electrode and a capping pattern, which are sequentially stacked on the semiconductor substrate across the device isolation layer pattern. The capping pattern includes a first gate contact hole that exposes a top surface of the gate electrode. An interlayer insulation layer pattern including a second gate contact hole is disposed to cover an entire surface of the semiconductor substrate including the gate electrode and the capping pattern. The second gate contact hole penetrates the first gate contact hole to expose the top surface of the gate electrode. A gate contact plug is disposed to be connected to the top surface of the gate electrode through the second gate contact hole. Accordingly, the interlayer insulation layer pattern is intervened between the gate contact plug and a sidewall of the capping pattern.

    Memory devices and method of manufacturing the same
    4.
    发明授权
    Memory devices and method of manufacturing the same 有权
    存储器件及其制造方法

    公开(公告)号：US08513136B2

    公开(公告)日：2013-08-20

    申请号：US13484999

    申请日：2012-05-31

    申请人： Doo-hwan Park ,  Gyu-hwan Oh ,  Dong-whee Kwon ,  Kyung-min Chung

    发明人： Doo-hwan Park ,  Gyu-hwan Oh ,  Dong-whee Kwon ,  Kyung-min Chung

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L45/06 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

    摘要： Memory devices and methods of forming memory devices including forming a plurality of preliminary electrodes, each of the plurality of preliminary electrodes including a protruding region, protruding from a first mold insulating layer, forming a second mold insulating layer on the first mold insulating layer, removing at least a portion of the plurality of preliminary electrodes to form a plurality of openings in the second mold insulating layer and a plurality of lower electrodes, and forming a plurality of memory elements in the plurality of openings. Memory devices and methods of forming memory devices including forming one or more insulating layers on sidewalls of all or part of a plurality of lower electrodes and/or a plurality of memory elements.

    摘要翻译： 存储器件和形成存储器件的方法包括形成多个预备电极，所述多个初步电极中的每一个包括从第一模绝缘层突出的突出区域，在第一模绝缘层上形成第二模绝缘层，去除 所述多个初步电极的至少一部分在所述第二模具绝缘层中形成多个开口，以及多个下部电极，并且在所述多个开口中形成多个存储元件。 存储器件和形成存储器件的方法包括在多个下部电极和/或多个存储器元件的全部或部分的侧壁上形成一个或多个绝缘层。

    MEMORY DEVICES AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    MEMORY DEVICES AND METHOD OF MANUFACTURING THE SAME 有权
    存储器件及其制造方法

    公开(公告)号：US20120305522A1

    公开(公告)日：2012-12-06

    申请号：US13484999

    申请日：2012-05-31

    申请人： Doo-hwan Park ,  Gyu-hwan Oh ,  Dong-whee Kwon ,  Kyung-min Chung

    发明人： Doo-hwan Park ,  Gyu-hwan Oh ,  Dong-whee Kwon ,  Kyung-min Chung

    IPC分类号： B05D5/12

    CPC分类号： H01L45/06 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

    摘要： Memory devices and methods of forming memory devices including forming a plurality of preliminary electrodes, each of the plurality of preliminary electrodes including a protruding region, protruding from a first mold insulating layer, forming a second mold insulating layer on the first mold insulating layer, removing at least a portion of the plurality of preliminary electrodes to form a plurality of openings in the second mold insulating layer and a plurality of lower electrodes, and forming a plurality of memory elements in the plurality of openings. Memory devices and methods of forming memory devices including forming one or more insulating layers on sidewalls of all or part of a plurality of lower electrodes and/or a plurality of memory elements.

    摘要翻译： 存储器件和形成存储器件的方法包括形成多个预备电极，所述多个初步电极中的每一个包括从第一模绝缘层突出的突出区域，在第一模绝缘层上形成第二模绝缘层，去除 所述多个初步电极的至少一部分在所述第二模具绝缘层中形成多个开口，以及多个下部电极，并且在所述多个开口中形成多个存储元件。 存储器件和形成存储器件的方法包括在多个下部电极和/或多个存储器元件的全部或部分的侧壁上形成一个或多个绝缘层。

    Gate-contact structure and method for forming the same
    6.
    发明申请
    Gate-contact structure and method for forming the same 失效
    栅极接触结构及其形成方法

    公开(公告)号：US20050118798A1

    公开(公告)日：2005-06-02

    申请号：US11029832

    申请日：2005-01-04

    申请人： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

    发明人： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

    IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L29/788 ,  H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L21/76895

    摘要： A gate-contact structure and a method for forming the same are provided. The structure includes a device isolation layer pattern formed at a semiconductor substrate to define an active region; and a gate electrode and a capping pattern, which are sequentially stacked on the semiconductor substrate across the device isolation layer pattern. The capping pattern includes a first gate contact hole that exposes a top surface of the gate electrode. An interlayer insulation layer pattern including a second gate contact hole is disposed to cover an entire surface of the semiconductor substrate including the gate electrode and the capping pattern. The second gate contact hole penetrates the first gate contact hole to expose the top surface of the gate electrode. A gate contact plug is disposed to be connected to the top surface of the gate electrode through the second gate contact hole. Accordingly, the interlayer insulation layer pattern is intervened between the gate contact plug and a sidewall of the capping pattern.

    摘要翻译： 提供了栅极接触结构及其形成方法。 该结构包括形成在半导体衬底上以限定有源区的器件隔离层图案; 以及栅电极和封盖图案，其跨越器件隔离层图案依次堆叠在半导体衬底上。 封盖图案包括暴露栅电极的顶表面的第一栅极接触孔。 设置包括第二栅极接触孔的层间绝缘层图案以覆盖包括栅电极和封盖图案的半导体衬底的整个表面。 第二栅极接触孔穿过第一栅极接触孔以暴露栅电极的顶表面。 栅极接触插头设置成通过第二栅极接触孔连接到栅电极的顶表面。 因此，层间绝缘层图案介于栅极接触插塞和封盖图案的侧壁之间。