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43 条记录 (耗时 0.035 秒)

    VARIABLE RESISTANCE NON-VOLATILE MEMORY CELLS AND METHODS OF FABRICATING SAME
    1.
    发明申请
    VARIABLE RESISTANCE NON-VOLATILE MEMORY CELLS AND METHODS OF FABRICATING SAME 失效
    可变电阻非挥发性记忆细胞及其制备方法

    公开(公告)号：US20080265236A1

    公开(公告)日：2008-10-30

    申请号：US11862779

    申请日：2007-09-27

    申请人： Jin-il Lee ,  Sung-Iae Cho ,  Hye-young Park ,  Byoung-Jae Bae ,  Young-Lim Park

    发明人： Jin-il Lee ,  Sung-Iae Cho ,  Hye-young Park ,  Byoung-Jae Bae ,  Young-Lim Park

    IPC分类号： H01L45/00

    CPC分类号： H01L27/2409 ,  G11C13/0004 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1683

    摘要： Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. Formation of an integrated circuit memory cell include forming a first electrode on a substrate. An insulation layer is formed on the substrate with an opening that exposes at least a portion of a first electrode. An amorphous variable resistivity material is formed on the first electrode and extends away from the first electrode along sidewalls of the opening. A crystalline variable resistivity material is formed in the opening on the amorphous variable resistivity material. A second electrode is formed on the crystalline variable resistivity material.

    摘要翻译： 公开了制造集成电路存储单元和集成电路存储单元的方法。 集成电路存储单元的形成包括在基板上形成第一电极。 在基板上形成具有露出第一电极的至少一部分的开口的绝缘层。 非晶可变电阻率材料形成在第一电极上，并沿着开口的侧壁远离第一电极延伸。 在非晶可变电阻率材料的开口中形成结晶可变电阻率材料。 在结晶可变电阻率材料上形成第二电极。

    Phase change memory device including resistant material
    3.
    发明授权
    Phase change memory device including resistant material 失效
    相变记忆装置，包括耐磨材料

    公开(公告)号：US07759667B2

    公开(公告)日：2010-07-20

    申请号：US11762801

    申请日：2007-06-14

    申请人： Young-Lim Park ,  Sung-Lae Cho ,  Byoung-Jae Bae ,  Jin-il Lee ,  Hye-Young Park ,  Ji-Eun Lim

    发明人： Young-Lim Park ,  Sung-Lae Cho ,  Byoung-Jae Bae ,  Jin-il Lee ,  Hye-Young Park ,  Ji-Eun Lim

    IPC分类号： H01L29/04

    CPC分类号： H01L45/148 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144 ,  H01L45/1691

    摘要： A phase change memory device includes a lower electrode provided on a substrate, an interlayer insulating layer including a contact hole exposing the lower electrode, and covering the substrate, a resistant material pattern filling the contact hole, a phase change pattern interposed between the resistant material pattern and the interlayer insulating layer, and extending between the resistant material pattern and the lower electrode, wherein the resistant material pattern has a higher resistance than the phase change pattern, and an upper electrode in contact with the phase change pattern, the upper electrode being electrically connected to the lower electrode through the phase change pattern.

    摘要翻译： 相变存储器件包括设置在基板上的下电极，包括暴露下电极的接触孔并覆盖基板的层间绝缘层，填充接触孔的电阻材料图案，插入在电阻材料之间的相变图案 图案和层间绝缘层，并且在电阻材料图案和下电极之间延伸，其中电阻材料图案具有比相变图案更高的电阻，以及与相变图案接触的上电极，上电极为 通过相变图案电连接到下电极。

    Variable resistance non-volatile memory cells and methods of fabricating same
    9.
    发明授权
    Variable resistance non-volatile memory cells and methods of fabricating same 失效
    可变电阻非易失性存储单元及其制造方法

    公开(公告)号：US07803654B2

    公开(公告)日：2010-09-28

    申请号：US11862779

    申请日：2007-09-27

    申请人： Jin-il Lee ,  Sung-lae Cho ,  Hye-young Park ,  Byoung-Jae Bae ,  Young-Lim Park

    发明人： Jin-il Lee ,  Sung-lae Cho ,  Hye-young Park ,  Byoung-Jae Bae ,  Young-Lim Park

    IPC分类号： H01L21/00

    CPC分类号： H01L27/2409 ,  G11C13/0004 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1683

    摘要： Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. Formation of an integrated circuit memory cell include forming a first electrode on a substrate. An insulation layer is formed on the substrate with an opening that exposes at least a portion of a first electrode. An amorphous variable resistivity material is formed on the first electrode and extends away from the first electrode along sidewalls of the opening. A crystalline variable resistivity material is formed in the opening on the amorphous variable resistivity material. A second electrode is formed on the crystalline variable resistivity material.

    摘要翻译： 公开了制造集成电路存储单元和集成电路存储单元的方法。 集成电路存储单元的形成包括在基板上形成第一电极。 在基板上形成具有露出第一电极的至少一部分的开口的绝缘层。 非晶可变电阻率材料形成在第一电极上，并沿着开口的侧壁远离第一电极延伸。 在非晶可变电阻率材料的开口中形成结晶可变电阻率材料。 在结晶可变电阻率材料上形成第二电极。