公开(公告)号：US08929123B2

公开(公告)日：2015-01-06

申请号：US13641832

申请日：2011-11-18

申请人： Jinfeng Kang ,  Feifei Zhang ,  Bin Gao ,  Bing Chen ,  Lifeng Liu ,  Xiaoyan Liu

发明人： Jinfeng Kang ,  Feifei Zhang ,  Bin Gao ,  Bing Chen ,  Lifeng Liu ,  Xiaoyan Liu

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083

摘要： The present disclosure provides a resistive-switching device capable of implementing multiary addition operation and a method for implementing multiary addition operation using the resistive-switching device. The resistive-switching device has a plurality of resistance values each corresponding to a respective data value stored by the resistive-switching device and ranging from a high resistance value to a low resistance value. The data value stored by the resistive-switching device is increased by ‘1’ successively with a series of set pulses having a same pulse width and a same voltage amplitude being applied thereto. The data value stored by the resistive-switching device is set to ‘0’ with a reset pulse being applied thereto, and meanwhile a data value stored by a higher-bit resistive-switching device is increased by ‘1’ with a set pulse being applied thereto. In this way, multiary addition operation is implemented.

摘要翻译： 本公开提供了一种能够实现多加法运算的电阻式开关装置和使用电阻式开关装置实现多重加法运算的方法。 电阻开关器件具有多个电阻值，每个电阻值对应于由电阻开关器件存储的各个数据值，并且从高电阻值到低电阻值。 由电阻式开关器件存储的数据值以相同的脉冲宽度和相同的电压幅度施加一系列设定脉冲连续增加“1”。 由施加复位脉冲的电阻开关器件存储的数据值被设定为“0”，同时由高位电阻开关器件存储的数据值增加“1”，设定脉冲为 应用于此。 以这种方式，实现多重添加操作。

公开(公告)号：US08924321B2

公开(公告)日：2014-12-30

申请号：US13502462

申请日：2011-11-03

申请人： Jinfeng Kang ,  Bin Gao ,  Feifei Zhang ,  Bing Chen ,  Lifeng Liu ,  Xiaoyan Liu

发明人： Jinfeng Kang ,  Bin Gao ,  Feifei Zhang ,  Bing Chen ,  Lifeng Liu ,  Xiaoyan Liu

IPC分类号： G06F15/18 ,  G06N3/00 ,  G06N3/063

CPC分类号： G06N3/063

摘要： A neuron device includes a bottom electrode, a top electrode, and a layer of metal oxide variable resistance material sandwiched between the bottom electrode and the top electrode, in which the neuron device is switched to a normal state upon application of reset pulse, and is switched to an excitation state upon application of stimulus pulses. The neuron device has a comprehensive response to different amplitude, different width of a stimulus voltage pulse and different number of a sequence of stimulus pulses, and provides functionalities of a weighting section and a computing section. The neuron device has a simple structure, excellent scalability, quick speed, low operation voltage, and is compatible with the conventional silicon-based CMOS fabrication process, and thus suitable for mass production. The neuron device is capable of performing many biological functions and complex logic operations.

摘要翻译： 神经元装置包括底部电极，顶部电极和夹在底部电极和顶部电极之间的金属氧化物可变电阻材料层，其中神经元装置在施加复位脉冲时切换到正常状态，并且是 在施加刺激脉冲时切换到激发状态。 神经元装置对刺激电压脉冲的不同幅度，不同宽度和不同数量的刺激脉冲序列具有综合响应，并提供加权部分和计算部分的功能。 神经元器件结构简单，可扩展性好，速度快，工作电压低，与传统的硅基CMOS制造工艺兼容，适合批量生产。 神经元器件能够执行许多生物学功能和复杂的逻辑运算。

公开(公告)号：US20130033922A1

公开(公告)日：2013-02-07

申请号：US13641832

申请日：2011-11-18

申请人： Jinfeng Kang ,  Feifei Zhang ,  Bin Gao ,  Bing Chen ,  Lifeng Liu ,  Xiaoyan Liu

发明人： Jinfeng Kang ,  Feifei Zhang ,  Bin Gao ,  Bing Chen ,  Lifeng Liu ,  Xiaoyan Liu

IPC分类号： H01L45/00 ,  G11C11/00

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083

摘要： The present disclosure provides a resistive-switching device capable of implementing multiary addition operation and a method for implementing multiary addition operation using the resistive-switching device. The resistive-switching device has a plurality of resistance values each corresponding to a respective data value stored by the resistive-switching device and ranging from a high resistance value to a low resistance value. The data value stored by the resistive-switching device is increased by ‘1’ successively with a series of set pulses having a same pulse width and a same voltage amplitude being applied thereto. The data value stored by the resistive-switching device is set to ‘0’ with a reset pulse being applied thereto, and meanwhile a data value stored by a higher-bit resistive-switching device is increased by ‘1’ with a set pulse being applied thereto. In this way, multiary addition operation is implemented. The operation of the resistive-switching device can implement data storage and the multiary addition operation simultaneously, and thus substantially simplifies the circuit structure. As a result, the data storage can be integrated with calculation.

摘要翻译： 本公开提供了一种能够实现多加法运算的电阻式开关装置和使用电阻式开关装置实现多重加法运算的方法。 电阻开关器件具有多个电阻值，每个电阻值对应于由电阻开关器件存储的各个数据值，并且从高电阻值到低电阻值。 由电阻式开关器件存储的数据值以连续的脉冲宽度与施加相同电压幅度的一系列设定脉冲连续增加1。 电阻开关器件存储的数据值被设置为0，并且施加复位脉冲，同时由施加了设定脉冲的高位电阻开关器件存储的数据值增加1。 以这种方式，实现多重添加操作。 电阻式开关器件的工作可以同时实现数据存储和多重加法运算，从而大大简化了电路结构。 因此，数据存储可以与计算集成。

公开(公告)号：US20120284218A1

公开(公告)日：2012-11-08

申请号：US13502462

申请日：2011-11-03

申请人： Jinfeng Kang ,  Bin Gao ,  Feifei Zhang ,  Bing Chen ,  Lifeng Liu ,  Xiaoyan Liu

发明人： Jinfeng Kang ,  Bin Gao ,  Feifei Zhang ,  Bing Chen ,  Lifeng Liu ,  Xiaoyan Liu

IPC分类号： G06N3/04 ,  H01L45/00

CPC分类号： G06N3/063

摘要： A neuron device includes a bottom electrode, a top electrode, and a layer of metal oxide variable resistance material sandwiched between the bottom electrode and the top electrode, in which the neuron device is switched to a normal state upon application of reset pulse, and is switched to an excitation state upon application of stimulus pulses. The neuron device has a comprehensive response to different amplitude, different width of a stimulus voltage pulse and different number of a sequence of stimulus pulses, and provides functionalities of a weighting section and a computing section. The neuron device has a simple structure, excellent scalability, quick speed, low operation voltage, and is compatible with the conventional silicon-based CMOS fabrication process, and thus suitable for mass production. The neuron device is capable of performing many biological functions and complex logic operations.

摘要翻译： 神经元装置包括底部电极，顶部电极和夹在底部电极和顶部电极之间的金属氧化物可变电阻材料层，其中神经元装置在施加复位脉冲时切换到正常状态，并且是 在施加刺激脉冲时切换到激发状态。 神经元装置对刺激电压脉冲的不同幅度，不同宽度和不同数量的刺激脉冲序列具有综合响应，并提供加权部分和计算部分的功能。 神经元器件结构简单，可扩展性好，速度快，工作电压低，与传统的硅基CMOS制造工艺兼容，适合批量生产。 神经元器件能够执行许多生物学功能和复杂的逻辑运算。

公开(公告)号：US09047937B2

公开(公告)日：2015-06-02

申请号：US13701626

申请日：2011-05-19

申请人： Jinfeng Kang ,  Bin Gao ,  Yuansha Chen ,  Bing Sun ,  Lifeng Liu ,  Xiaoyan Liu

发明人： Jinfeng Kang ,  Bin Gao ,  Yuansha Chen ,  Bing Sun ,  Lifeng Liu ,  Xiaoyan Liu

IPC分类号： G11C11/00 ,  G11C11/36 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC分类号： G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1253 ,  H01L45/16 ,  H01L45/1608

摘要： A resistive random access memory device, a method for manufacturing the resistive random access memory device, and a method for operating the resistive random access memory device are disclosed. The resistive random access memory device includes a resistive switching memory element including two electrodes and a layer of variable-resistance material between the two electrodes, wherein the layer of variable-resistance material exhibits bipolar resistive switching behavior; and a Schottky diode including a metal layer and a p-doped semiconductor layer which contact each other, wherein the metal layer of the Schottky diode is coupled to one of the two electrodes of the resistive switching memory element. The present disclosure provides the resistive random access memory device operating in bipolar resistive switching scheme.

摘要翻译： 公开了电阻随机存取存储器件，制造电阻随机存取存储器件的方法和用于操作电阻随机存取存储器件的方法。 电阻式随机存取存储器件包括电阻式开关存储元件，该电阻开关存储器元件包括两个电极和两个电极之间的可变电阻材料层，其中该可变电阻材料层具有双极电阻开关行为; 以及包括彼此接触的金属层和p掺杂半导体层的肖特基二极管，其中所述肖特基二极管的金属层耦合到所述电阻式开关存储元件的两个电极中的一个。 本公开提供了在双极性电阻式交换方案中工作的电阻随机存取存储器件。

公开(公告)号：US20130128653A1

公开(公告)日：2013-05-23

申请号：US13701626

申请日：2011-05-19

申请人： Jinfeng Kang ,  Bin Gao ,  Yuansha Chen ,  Bing Sun ,  Lifeng Liu ,  Xiaoyan Liu

发明人： Jinfeng Kang ,  Bin Gao ,  Yuansha Chen ,  Bing Sun ,  Lifeng Liu ,  Xiaoyan Liu

IPC分类号： G11C13/00 ,  H01L45/00

CPC分类号： G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1253 ,  H01L45/16 ,  H01L45/1608

摘要： A resistive random access memory device, a method for manufacturing the resistive random access memory device, and a method for operating the resistive random access memory device are disclosed. The resistive random access memory device includes a resistive switching memory element including two electrodes and a layer of variable-resistance material between the two electrodes, wherein the layer of variable-resistance material exhibits bipolar resistive switching behavior; and a Schottky diode including a metal layer and a p-doped semiconductor layer which contact each other, wherein the metal layer of the Schottky diode is coupled to one of the two electrodes of the resistive switching memory element. The present disclosure provides the resistive random access memory device operating in bipolar resistive switching scheme.

摘要翻译： 公开了电阻随机存取存储器件，制造电阻随机存取存储器件的方法和用于操作电阻随机存取存储器件的方法。 电阻式随机存取存储器件包括电阻式开关存储元件，该电阻开关存储器元件包括两个电极和两个电极之间的可变电阻材料层，其中该可变电阻材料层具有双极电阻开关行为; 以及包括彼此接触的金属层和p掺杂半导体层的肖特基二极管，其中所述肖特基二极管的金属层耦合到所述电阻式开关存储元件的两个电极中的一个。 本公开提供了在双极性电阻式交换方案中工作的电阻随机存取存储器件。

公开(公告)号：US08552754B2

公开(公告)日：2013-10-08

申请号：US13113513

申请日：2011-05-23

申请人： Xiaoyan Liu ,  Jiaqi Yang ,  Jinfeng Kang ,  Jingfeng Yang ,  Bing Chen

发明人： Xiaoyan Liu ,  Jiaqi Yang ,  Jinfeng Kang ,  Jingfeng Yang ,  Bing Chen

IPC分类号： G01R31/00

CPC分类号： G01R31/2621 ,  G01R31/2642

摘要： The invention provides a method of testing reliability of a semiconductor device, wherein the semiconductor device has negative bias temperature instability NBTI. The method comprises steps of: measuring a NBTI curve of a first set of semiconductor devices; measuring 1/f noise power spectrum density and drain current at a predetermined frequency for the first set of the semiconductor devices, under a condition that the first set of the semiconductor devices are biased at a gate electric field; measuring an equivalent oxide thickness EOT of gate dielectric of the first set of the semiconductor devices; measuring 1/f noise power spectrum density and drain current at the predetermined frequency for a second set of semiconductor devices, under a condition that the second set of the semiconductor devices are biased at the gate electric field; measuring an EOT of gate dielectric of the second set of the semiconductor devices; and evaluating a degradation characteristic of the second set of the semiconductor devices by using the NBTI curve of a first set of the semiconductor devices. The method saves the time required for testing the reliability of a large numbers of semiconductor devices, and will not cause damages to the second set of semiconductor devices.

摘要翻译： 本发明提供一种测试半导体器件的可靠性的方法，其中半导体器件具有负偏压温度不稳定性NBTI。 该方法包括以下步骤：测量第一组半导体器件的NBTI曲线; 在第一组半导体器件被偏置在栅极电场的条件下，测量用于第一组半导体器件的预定频率的1 / f噪声功率谱密度和漏极电流; 测量第一组半导体器件的栅极电介质的等效氧化物厚度EOT; 在第二组半导体器件偏置在栅极电场的条件下，测量第二组半导体器件的预定频率处的1 / f噪声功率谱密度和漏极电流; 测量所述第二组半导体器件的栅极电介质的EOT; 以及通过使用第一组半导体器件的NBTI曲线来评估第二组半导体器件的劣化特性。 该方法节省了测试大量半导体器件的可靠性所需的时间，并且不会对第二组半导体器件造成损害。

公开(公告)号：US20120299608A1

公开(公告)日：2012-11-29

申请号：US13113513

申请日：2011-05-23

申请人： Xiaoyan Liu ,  Jiaqi Yang ,  Jinfeng Kang ,  Jingfeng Yang ,  Bing Chen

发明人： Xiaoyan Liu ,  Jiaqi Yang ,  Jinfeng Kang ,  Jingfeng Yang ,  Bing Chen

IPC分类号： G01R31/26

CPC分类号： G01R31/2621 ,  G01R31/2642

摘要： The invention provides a method of testing reliability of a semiconductor device, wherein the semiconductor device has negative bias temperature instability NBTI. The method comprises steps of: measuring a NBTI curve of a first set of semiconductor devices; measuring 1/f noise power spectrum density and drain current at a predetermined frequency for the first set of the semiconductor devices, under a condition that the first set of the semiconductor devices are biased at a gate electric field; measuring an equivalent oxide thickness EOT of gate dielectric of the first set of the semiconductor devices; measuring 1/f noise power spectrum density and drain current at the predetermined frequency for a second set of semiconductor devices, under a condition that the second set of the semiconductor devices are biased at the gate electric field; measuring an EOT of gate dielectric of the second set of the semiconductor devices; and evaluating a degradation characteristic of the second set of the semiconductor devices by using the NBTI curve of a first set of the semiconductor devices. The method saves the time required for testing the reliability of a large numbers of semiconductor devices, and will not cause damages to the second set of semiconductor devices.

摘要翻译： 本发明提供一种测试半导体器件的可靠性的方法，其中半导体器件具有负偏压温度不稳定性NBTI。 该方法包括以下步骤：测量第一组半导体器件的NBTI曲线; 在第一组半导体器件被偏置在栅极电场的条件下，测量用于第一组半导体器件的预定频率的1 / f噪声功率谱密度和漏极电流; 测量第一组半导体器件的栅极电介质的等效氧化物厚度EOT; 在第二组半导体器件偏置在栅极电场的条件下，测量第二组半导体器件的预定频率处的1 / f噪声功率谱密度和漏极电流; 测量所述第二组半导体器件的栅极电介质的EOT; 以及通过使用第一组半导体器件的NBTI曲线来评估第二组半导体器件的劣化特性。 该方法节省了测试大量半导体器件的可靠性所需的时间，并且不会对第二组半导体器件造成损害。

公开(公告)号：US20120298199A1

公开(公告)日：2012-11-29

申请号：US13116779

申请日：2011-05-26

申请人： Jinfeng Kang ,  Bao Wang ,  Xu Wang ,  Tianshu Zhang ,  Ziqing Lu ,  Yan Wang ,  Xiaoyan Liu

发明人： Jinfeng Kang ,  Bao Wang ,  Xu Wang ,  Tianshu Zhang ,  Ziqing Lu ,  Yan Wang ,  Xiaoyan Liu

IPC分类号： H01L31/0296 ,  H01L31/18

CPC分类号： H01G9/2054 ,  H01G9/2031 ,  H01G9/2059 ,  H01G9/2063 ,  Y02E10/542 ,  Y02P70/521

摘要： A solar cell includes a cathode component, an anode component, sealant for assembling the cathode component and the anode component to form a closed space, and electrolyte accommodated in the closed space, in which the cathode component contains a lower transparent conductive substrate, a nano-oxide semiconductor thin film formed on the lower transparent conductive substrate, and dye attached to a nano-particle surface of the nano-oxide semiconductor thin film; and the anode component contains an upper transparent conductive substrate, and an anode electrode layer formed on the upper transparent conductive substrate, the nano-oxide semiconductor thin film and the anode electrode layer being arranged opposite to each other and contacting with the electrolyte, in which the anode component further contains a CdTe layer which is patterned to have an opening, and the anode electrode layer is located in the opening of the CdTe layer.

摘要翻译： 太阳能电池包括阴极部件，阳极部件，用于组装阴极部件和阳极部件以形成封闭空间的密封剂和容纳在封闭空间中的电解质，其中阴极部件包含下部透明导电基板，纳米 形成在下部透明导电性基板上的氧化物半导体薄膜和附着在纳米氧化物半导体薄膜的纳米粒子表面的染料; 并且所述阳极部件包含上部透明导电性基板，形成在所述上部透明导电性基板上的所述阳极电极层，所述纳米氧化物半导体薄膜和所述阳极电极层相对配置并与所述电解液接触， 阳极部件还包含被图案化以具有开口的CdTe层，并且阳极电极层位于CdTe层的开口中。