Systems and methods for retimed virtual data processing
    1.
    发明授权
    Systems and methods for retimed virtual data processing 有权
    重新定义虚拟数据处理的系统和方法

    公开(公告)号:US08413020B2

    公开(公告)日:2013-04-02

    申请号:US13570050

    申请日:2012-08-08

    IPC分类号: H03M13/00

    摘要: Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples.

    摘要翻译: 本发明的各种实施例提供了用于数据处理系统的系统和方法。 作为一个示例,描述了包括模数转换器,在线定时循环和离线定时循环的数据处理电路。 模数转换器接收模拟输入并提供第一系列数据样本第一系列数据采样的每一位对应于在更新的采样时钟控制的时间的模拟输入。 在线定时循环至少部分地基于第一系列数据样本的处理版本来修改更新的采样时钟。

    Systems and Methods for Retimed Virtual Data Processing
    2.
    发明申请
    Systems and Methods for Retimed Virtual Data Processing 有权
    Retimed虚拟数据处理的系统和方法

    公开(公告)号:US20120324307A1

    公开(公告)日:2012-12-20

    申请号:US13570050

    申请日:2012-08-08

    IPC分类号: G06F1/08 G06F11/10

    摘要: Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples.

    摘要翻译: 本发明的各种实施例提供了用于数据处理系统的系统和方法。 作为一个示例,描述了包括模数转换器,在线定时循环和离线定时循环的数据处理电路。 模数转换器接收模拟输入并提供第一系列数据样本第一系列数据采样的每一位对应于在更新的采样时钟控制的时间的模拟输入。 在线定时循环至少部分地基于第一系列数据样本的处理版本来修改更新的采样时钟。

    Systems and methods for auto scaling in a data processing system
    3.
    发明授权
    Systems and methods for auto scaling in a data processing system 有权
    用于数据处理系统中自动缩放的系统和方法

    公开(公告)号:US08854753B2

    公开(公告)日:2014-10-07

    申请号:US13050129

    申请日:2011-03-17

    摘要: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit having a data detection circuit is disclosed that includes: a scaling circuit, a soft output calculation circuit, and a factor calculation circuit. The scaling circuit is operable to scale a branch metric value by a scaling factor to yield a scaled output. The soft output calculation circuit is operable to calculate a soft output based at least in part on the scaled output. The factor calculation circuit operable to modify the scaling factor based at least in part on the soft output.

    摘要翻译: 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例,公开了具有数据检测电路的数据处理电路,其包括:缩放电路,软输出计算电路和因子计算电路。 缩放电路可操作以通过缩放因子缩放分支度量值以产生缩放的输出。 软输出计算电路可操作以至少部分地基于缩放的输出来计算软输出。 因子计算电路可操作以至少部分地基于软输出来修改缩放因子。

    Detector for low frequency offset distortion
    4.
    发明授权
    Detector for low frequency offset distortion 失效
    低频偏移失真检测器

    公开(公告)号:US08537883B1

    公开(公告)日:2013-09-17

    申请号:US13365712

    申请日:2012-02-03

    IPC分类号: H03H7/30

    摘要: A system for removing low frequency offset distortion from a digital signal, the system comprising an analog-to-digital converter to convert an analog frequency signal associated with an optical storage medium to a digital frequency signal; an equalizer to equalize the digital frequency signal; an estimator to estimate a low frequency offset distortion of the digital frequency signal; a compensator to substantially cancel the low frequency offset distortion of the digital frequency signal from the equalized digital frequency signal using the estimate; and a decoder to decode the equalized digital frequency signal having the low frequency offset distortion substantially cancelled therefrom.

    摘要翻译: 一种用于从数字信号中去除低频偏移失真的系统,该系统包括用于将与光学存储介质相关联的模拟频率信号转换为数字频率信号的模拟 - 数字转换器; 均衡器以均衡数字频率信号; 用于估计数字频率信号的低频偏移失真的估计器; 补偿器,用于使用所述估计从所述均衡数字频率信号基本上消除所述数字频率信号的低频偏移失真; 以及解码器,用于解码具有基本上从其中抵消的低频偏移失真的均衡数字频率信号。

    Error correction capability adjustment of LDPC codes for storage device testing
    5.
    发明授权
    Error correction capability adjustment of LDPC codes for storage device testing 失效
    用于存储设备测试的LDPC码的纠错能力调整

    公开(公告)号:US08413029B2

    公开(公告)日:2013-04-02

    申请号:US12402359

    申请日:2009-03-11

    IPC分类号: H03M13/03 G11C29/00

    摘要: Methods and structure described herein provide for adjusting an error correction capability of an LDPC error correction code. For example, the system of one embodiment includes a decoder adapted to decode data that has been encoded with a LDPC error correction code. The system also includes a detector communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit value estimations to reduce the error correction capability of the LDPC error correction code. The reduction in error correction capability is adjustable such that sector failure rates of storage devices may be incrementally analyzed.

    摘要翻译: 本文描述的方法和结构提供了用于调整LDPC纠错码的纠错能力。 例如,一个实施例的系统包括适于对已经用LDPC纠错码编码的数据进行解码的解码器。 该系统还包括通信地耦合到解码器并且适于在解码器解码之前估计数据中的位值的检测器。 检测器还适于基于比特值估计改变比特值,以减少LDPC纠错码的纠错能力。 误差校正能力的降低是可调节的,从而可以逐渐分析存储设备的扇区故障率。

    Read Channel With Oversampled Analog To Digital Conversion And Parallel Data Detectors
    6.
    发明申请
    Read Channel With Oversampled Analog To Digital Conversion And Parallel Data Detectors 审中-公开
    读取通道与过采样模数转换和并行数据检测器

    公开(公告)号:US20130050005A1

    公开(公告)日:2013-02-28

    申请号:US13215815

    申请日:2011-08-23

    IPC分类号: H03M1/12

    摘要: Methods and apparatus are provided for processing a signal in a read channel using a selective oversampled analog to digital conversion. The disclosed selective oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain. An oversampled analog to digital conversion is applied to an analog input signal to generate a plurality of digital samples for a given bit interval. The plurality of digital samples for a given bit interval are applied to a corresponding plurality of data detectors to obtain a detected output. The plurality of digital samples for a given bit interval may have a phase offset relative to one another. The detected output may be obtained, for example, by summing the outputs of the plurality of data detectors or by aggregating weighted outputs of the plurality of data detectors.

    摘要翻译: 提供了用于使用选择性过采样模数转换处理读通道中的信号的方法和装置。 所公开的选择性过采样模数转换通过将均衡和/或滤波处理的至少一部分转移到数字域来简化了模拟设计。 将过采样的模数转换应用于模拟输入信号,以产生给定位间隔的多个数字采样。 将给定位间隔的多个数字样本应用于相应的多个数据检测器以获得检测到的输出。 给定比特间隔的多个数字样本可以具有相对于彼此的相位偏移。 检测的输出可以例如通过对多个数据检测器的输出求和或者通过聚合多个数据检测器的加权输出来获得。

    Defect detection design
    7.
    发明授权
    Defect detection design 有权
    缺陷检测设计

    公开(公告)号:US08315132B1

    公开(公告)日:2012-11-20

    申请号:US13235658

    申请日:2011-09-19

    IPC分类号: G11B15/52

    摘要: A system and method are provided to detect defects in a data storage medium by sampling data read from the data storage medium. Time referenced samples of data read from the data storage medium are equalized to mediate the effects of channel noise and the equalized samples are decoded by a decoder, such as a Viterbi decoder. The decoded signal is then reconstructed through a reconstruction filter to approximate the equalized signal. The equalized data signal and the reconstructed data signal are then combined and compared in a bit-by-bit deconstruction scheme to determine, based on a variation between the signal elements, that a defect exists on the data storage medium. Additional action is then taken to mediate the effects of attempting to process corrupted data based on the defect by isolating the defective bit.

    摘要翻译: 提供了一种系统和方法,用于通过对从数据存储介质读取的数据进行采样来检测数据存储介质中的缺陷。 将从数据存储介质读取的数据的时间参考样本相等以调解信道噪声的影响,并且均衡样本由诸如维特比解码器之类的解码器解码。 然后通过重建滤波器重建经解码的信号以近似均衡的信号。 然后将均衡的数据信号和重建的数据信号以逐位解构方案进行组合和比较,以基于信号元素之间的变化来确定数据存储介质上存在缺陷。 然后采取额外的行动来通过隔离有缺陷的位来调解基于缺陷来处理被破坏的数据的效果。

    Systems and methods for format efficient calibration for servo data based harmonics calculation
    8.
    发明授权
    Systems and methods for format efficient calibration for servo data based harmonics calculation 失效
    基于伺服数据的谐波计算格式有效校准的系统和方法

    公开(公告)号:US08300349B2

    公开(公告)日:2012-10-30

    申请号:US12851425

    申请日:2010-08-05

    IPC分类号: G11B21/02 G11B5/09

    摘要: Various embodiments of the present invention provide systems and methods for servo data based harmonics calculation. For example, a method for calculating harmonics is disclosed that includes: providing a data processing circuit; receiving a first data set derived from a data source during a servo data processing period; performing a first harmonics calculation using the first data set to yield a first harmonics ratio; receiving a second data set derived from a source other than the previously mentioned data source during a user data processing period; performing a second harmonics calculation using the second data set to yield a second harmonics ratio; and calculating a ratio of the first harmonics ratio to the second harmonics ratio.

    摘要翻译: 本发明的各种实施例提供了用于基于伺服数据的谐波计算的系统和方法。 例如,公开了一种用于计算谐波的方法,包括:提供数据处理电路; 在伺服数据处理期间接收从数据源导出的第一数据组; 使用所述第一数据组执行第一谐波计算以产生第一谐波比; 在用户数据处理期间接收从除了前述数据源之外的源得到的第二数据集; 使用所述第二数据组执行二次谐波计算以产生第二谐波比; 以及计算所述第一谐波比与所述第二谐波比的比率。

    Systems and methods for low latency noise cancellation
    9.
    发明授权
    Systems and methods for low latency noise cancellation 有权
    用于低延迟噪声消除的系统和方法

    公开(公告)号:US08295001B2

    公开(公告)日:2012-10-23

    申请号:US12887369

    申请日:2010-09-21

    IPC分类号: G11B5/09 G11B27/36

    CPC分类号: G11B20/10046 G11B20/10509

    摘要: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes a data detector circuit, a detector mimicking circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The data mimicking circuit is operable to process a second signal derived from the data input to yield a mimicked output. The error calculation circuit is operable to calculate a difference between the second signal and a third signal derived from the mimicked output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.

    摘要翻译: 本发明的各种实施例提供了用于数据处理的系统和方法。 例如,讨论了包括数据检测器电路,检测器模拟电路和误差计算电路的数据处理电路。 数据检测器电路可操作以对从数据输入导出的第一信号执行数据检测处理,以产生检测到的输出。 数据模拟电路可操作以处理从数据输入得到的第二信号以产生模拟输出。 误差计算电路可用于计算第二信号和从模拟输出得到的第三信号之间的差以产生反馈信号。 反馈信号可操作以在随后的时段内修改数据输入。

    Systems and Methods for Auto Scaling in a Data Processing System
    10.
    发明申请
    Systems and Methods for Auto Scaling in a Data Processing System 有权
    数据处理系统中自动缩放的系统和方法

    公开(公告)号:US20120236430A1

    公开(公告)日:2012-09-20

    申请号:US13050129

    申请日:2011-03-17

    IPC分类号: G11B5/09

    摘要: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit having a data detection circuit is disclosed that includes: a scaling circuit, a soft output calculation circuit, and a factor calculation circuit. The scaling circuit is operable to scale a branch metric value by a scaling factor to yield a scaled output. The soft output calculation circuit is operable to calculate a soft output based at least in part on the scaled output. The factor calculation circuit operable to modify the scaling factor based at least in part on the soft output.

    摘要翻译: 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例,公开了具有数据检测电路的数据处理电路,其包括:缩放电路,软输出计算电路和因子计算电路。 缩放电路可操作以通过缩放因子缩放分支度量值以产生缩放的输出。 软输出计算电路可操作以至少部分地基于缩放的输出来计算软输出。 因子计算电路可操作以至少部分地基于软输出来修改缩放因子。