公开(公告)号：US20130093533A1

公开(公告)日：2013-04-18

申请号：US13272802

申请日：2011-10-13

Applicant: Tiku Yu ,  Jing-Hong Conan Zhan

Inventor： Tiku Yu ,  Jing-Hong Conan Zhan

IPC: H01P5/12

CPC classification number: H01P5/16

Abstract: An M-way coupler having a first port, M second ports, M transmission line sections, M isolation resistors and a phase shifting network is disclosed, where M is an integer number greater than 1. The M transmission line sections couple the first port to the M second ports, respectively. Each of the M isolation resistors has a first terminal and a second terminal. The first terminals of the M isolation resistors are coupled to the M second ports, respectively. The phase shifting network has M I/O terminals coupled to the second terminals of the M isolation resistors, respectively. The phase shifting network is arranged to provide a phase shift within a predetermined tolerance margin between arbitrary two I/O terminals of the M I/O terminals of the phase shifting network.

Abstract translation: 公开了具有第一端口，M个第二端口，M个传输线路段，M个隔离电阻器和一个移相网络的M路耦合器，其中M是大于1的整数.M个传输线段将第一端口耦合到 M个第二个端口。 每个M个隔离电阻具有第一端子和第二端子。 M个隔离电阻器的第一个端子分别耦合到M个第二端口。 相移网络具有分别耦合到M个隔离电阻器的第二端子的M I / O端子。 相移网络被布置成在相移网络的M I / O端子的任意两个I / O端子之间提供预定容限裕度内的相移。

公开(公告)号：US20120133404A1

公开(公告)日：2012-05-31

申请号：US13095873

申请日：2011-04-28

Applicant: Yu-Li Hsueh ,  Yi-Hsien Cho ,  Jing-Hong Conan Zhan

Inventor： Yu-Li Hsueh ,  Yi-Hsien Cho ,  Jing-Hong Conan Zhan

IPC: H03L7/06

CPC classification number: H03L5/00 ,  H03L7/089 ,  H03L7/0895 ,  H03L7/0896 ,  H03L7/093

Abstract: A charge pump being disposed in a phase locking system. The charge pump includes a sourcing element, a draining element and an offset element. The sourcing element is arranged to selectively source a first current into an output terminal of the charge pump according to a first control signal, and the draining element is arranged to selectively drain a second current from the output terminal according to a second control signal. The offset element is arranged to selectively conduct an offset current via the output terminal according to a third control signal, and one of the sourcing element and the draining element is disabled when the phase locking system is in a phase-locked state.

Abstract translation: 电荷泵设置在相位锁定系统中。 电荷泵包括源元件，排液元件和偏移元件。 源极元件被布置成根据第一控制信号选择性地将第一电流源流到电荷泵的输出端，并且排水元件被布置成根据第二控制信号从输出端选择性地排出第二电流。 偏移元件布置成根据第三控制信号经由输出端选择性地导通偏移电流，并且当锁相系统处于锁相状态时，源元件和排液元件之一被禁用。

公开(公告)号：US20090261876A1

公开(公告)日：2009-10-22

申请号：US12107196

申请日：2008-04-22

Applicant: Jing-Hong Conan Zhan

Inventor： Jing-Hong Conan Zhan

IPC: H03L7/06 ,  H03B7/06

CPC classification number: H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124

Abstract: An embodiment of the voltage controlled oscillator is provided. The oscillator comprises a first inductor set, a second inductor set, a second capacitor, a voltage source and a negative resistance element. The inductance of the second inductor set is k times the inductance of the first inductor set. The voltage source applies an ac voltage to the second inductor set. The negative resistance element is coupled to the second inductor set to provide a negative resistance to resonate the second capacitor at the second inductor set.

Abstract translation: 提供了压控振荡器的实施例。 振荡器包括第一电感器组，第二电感器组，第二电容器，电压源和负电阻元件。 第二电感器组的电感为第一电感器组的电感的k倍。 电压源对第二电感器组施加交流电压。 负电阻元件耦合到第二电感器组，以提供负电阻以在第二电感器组谐振第二电容器。

公开(公告)号：US20090096539A1

公开(公告)日：2009-04-16

申请号：US12235624

申请日：2008-09-23

Applicant: Hsiang-Hui Chang ,  Bing-Yu Hsieh ,  Jing-Hong Conan Zhan

Inventor： Hsiang-Hui Chang ,  Bing-Yu Hsieh ,  Jing-Hong Conan Zhan

IPC: H03L7/085 ,  H03M13/00

CPC classification number: H03L7/085 ,  H03L7/0991 ,  H03L2207/50

Abstract: An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.

Abstract translation: 错误预测码被添加到周期信号中，以提高时间数字（TDC）解码器的输出信号的精度。 在全数字锁相环（ADPLL）的相位频率检测器（PFD）/ CTDC模块中专门设计了循环TDC（CTDC），用于增强ADPLL的环路带宽校准。 在PFD / CTDC模块上使用校准方法，以增强ADPLL的环路带宽校准。

公开(公告)号：US20090096538A1

公开(公告)日：2009-04-16

申请号：US12235615

申请日：2008-09-23

Applicant: Hsiang-Hui Chang ,  Ping-Ying Wang ,  Jing-Hong Conan Zhan ,  Bing-Yu Hsieh

Inventor： Hsiang-Hui Chang ,  Ping-Ying Wang ,  Jing-Hong Conan Zhan ,  Bing-Yu Hsieh

IPC: H03L7/08

CPC classification number: H03L7/085 ,  H03L7/0991 ,  H03L2207/50

Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

Abstract translation: 为了减少模拟锁相环中的误差，使用具有数字组件和数字操作的全数字锁相环（ADPLL）。 ADPLL也可用于直接调频（DFM）。 通过将ADPLL的比例路径增益定义为ADPLL的带宽和参考频率，通过TDC增益，DCO增益，分频器的分频比，放大器的增益或其组合，增益 可以调整放大器，使得可以良好校准ADPLL的最佳环路带宽。 为了达到ADPLL完全数字化的目的，TDC和DCO的收益可能会以数字方式进一步调整。

公开(公告)号：US06496126B2

公开(公告)日：2002-12-17

申请号：US09981861

申请日：2001-10-17

Applicant: Jing-Hong Conan Zhan ,  Andrew C. Chang ,  Chi-Kwong Ho

Inventor： Jing-Hong Conan Zhan ,  Andrew C. Chang ,  Chi-Kwong Ho

IPC: H03M136

CPC classification number: G11B20/10 ,  G11B7/005 ,  H03K5/086

Abstract: A data slice circuit and the method thereof The data slice circuit comprises a digitizer, a finite state machine, and a digitizer parameter adjustment element. The digitizer receives an analog signal and converts to a digital signal. The finite state machine generates a state signal in response to the digital signal. The digitizer parameter adjustment element generates a parameter adjustment signal in response to the state signal from the finite state machine. The digital signal of the digitizer is adjusted in accordance with the parameter adjustment signal.

Abstract translation: 数据切片电路及其方法数据切片电路包括数字转换器，有限状态机和数字转换器参数调整元件。 数字化仪接收模拟信号并转换为数字信号。 有限状态机响应于数字信号产生状态信号。 数字转换器参数调整元件响应来自有限状态机的状态信号产生参数调整信号。 数字转换器的数字信号根据参数调整信号进行调整。

公开(公告)号：US09088448B2

公开(公告)日：2015-07-21

申请号：US13612811

申请日：2012-09-12

Applicant: Sean Timothy Nicolson ,  ChuanKang Liang ,  Jing-Hong Conan Zhan

Inventor： Sean Timothy Nicolson ,  ChuanKang Liang ,  Jing-Hong Conan Zhan

IPC: H03H7/30 ,  H04L25/03 ,  H01Q3/26

CPC classification number: H04B17/14 ,  H01Q3/267 ,  H04B7/04 ,  H04L25/03878

Abstract: The calibration method, performed on a phased array device including channel elements coupled in parallel by a transmission line, has the steps of: obtaining channel responses corresponding to the channel elements through the transmission line, and each of the channel responses is obtained when one of the channel elements is turned on, and the rest of the channel elements are turned off; calculating a characteristic value corresponding to the transmission line based on the obtained channel responses of the channel elements; and adjusting a channel parameter of one of the channel elements based on the characteristic value of the transmission line.

Abstract translation: 在包括通过传输线并联耦合的信道单元的相控阵器件上执行的校准方法具有以下步骤：通过传输线获得对应于信道单元的信道响应，并且当以下之一获得每个信道响应时 通道元件接通，其余通道元件关闭; 基于所获得的信道要素的信道响应，计算与所述传输线对应的特征值; 以及基于所述传输线的特征值来调整所述信道单元之一的信道参数。

公开(公告)号：US08878582B2

公开(公告)日：2014-11-04

申请号：US13612729

申请日：2012-09-12

Applicant: Yu-Li Hsueh ,  Chih-Hsien Shen ,  Jing-Hong Conan Zhan

Inventor： Yu-Li Hsueh ,  Chih-Hsien Shen ,  Jing-Hong Conan Zhan

IPC: H03K3/017 ,  H03K5/156

CPC classification number: H03K3/017 ,  H03K5/1565

Abstract: An apparatus for duty cycle calibration includes an input calibration circuit, a delay chain, a first comparator, and a second comparator. The input calibration circuit calibrates an input clock signal according to a first control signal so as to generate an input calibration clock signal. The delay chain includes a plurality of delay units coupled in series, and delays the input calibration clock signal so as to generate a first delay clock signal and a second delay clock signal. At least two of the delay units each have an adjustable delay time which is controlled according to a second control signal. The first comparator compares the input calibration clock signal with the first delay clock signal so as to generate the first control signal. The second comparator compares the input calibration clock signal with the second delay clock signal so as to generate the second control signal.

Abstract translation: 用于占空比校准的装置包括输入校准电路，延迟链，第一比较器和第二比较器。 输入校准电路根据第一控制信号校准输入时钟信号，以产生输入校准时钟信号。 延迟链包括串联耦合的多个延迟单元，并延迟输入校准时钟信号，以产生第一延迟时钟信号和第二延迟时钟信号。 延迟单元中的至少两个具有根据第二控制信号来控制的可调延迟时间。 第一比较器将输入校准时钟信号与第一延迟时钟信号进行比较，以产生第一控制信号。 第二比较器将输入校准时钟信号与第二延迟时钟信号进行比较，以产生第二控制信号。

公开(公告)号：US08429487B2

公开(公告)日：2013-04-23

申请号：US12982918

申请日：2010-12-31

Applicant: Hsiang-Hui Chang ,  Bing-Yu Hsieh ,  Jing-Hong Conan Zhan

Inventor： Hsiang-Hui Chang ,  Bing-Yu Hsieh ,  Jing-Hong Conan Zhan

IPC: H03M13/00

CPC classification number: H03L7/085 ,  H03L7/0991 ,  H03L2207/50

Abstract: An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits.

Abstract translation: 用于全数字锁相环（ADPLL）的时间 - 数字转换器（TDC）解码器的误差保护方法包括：检索由TDC解码器接收的数字码; 检索由TDC解码器接收的周期代码; 对数字代码的第一预定位执行异或运算，以及循环码的第二预定位用于产生错误保护代码; 并且通过将错误保护代码添加到周期代码中并将循环码移位第三预定位数，并使用错误保护代码来修正周期代码内的错误。

公开(公告)号：US20120294338A1

公开(公告)日：2012-11-22

申请号：US13301811

申请日：2011-11-22

Applicant: Jing-Hong Conan Zhan ,  Chuan-Kang Liang ,  Ti-Ku Yu ,  Zhiming Deng

Inventor： Jing-Hong Conan Zhan ,  Chuan-Kang Liang ,  Ti-Ku Yu ,  Zhiming Deng

IPC: H04B1/38

CPC classification number: H04B1/40 ,  H01Q3/30 ,  H01Q21/0025 ,  H03F3/19 ,  H03F3/21 ,  H03F2200/294 ,  H03F2200/451 ,  H04B1/44

Abstract: A phased-array transceiver includes: a plurality of antennas; a plurality of transceiving elements respectively coupled to the plurality of antennas, at least one of the transceiving elements comprising a first transmitting circuit and a first receiving circuit; a signal processing block; and a first distributed network, coupled between the signal processing block and the transceiving elements, wherein the transceiving elements, the signal processing block, and the first distributed network are configured as a single chip, and a first path from the antenna through the first receiving circuit to the signal processing block and a second path from the signal processing block through the first transmitting circuit to the antenna share at least partial signal traces of the phased-array transceiver.

Abstract translation: 相控阵收发器包括：多个天线; 分别耦合到所述多个天线的多个收发元件，所述收发元件中的至少一个包括第一发送电路和第一接收电路; 信号处理块; 以及耦合在所述信号处理块和所述收发元件之间的第一分布式网络，其中所述收发元件，所述信号处理块和所述第一分布式网络被配置为单个芯片，以及从所述天线通过所述第一接收的第一路径 信号处理块的电路和从信号处理块通过第一发送电路到天线的第二路径共享相控阵收发器的至少部分信号迹线。