Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials
    3.
    发明授权
    Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials 失效
    用于DRAM的多层Pt电极和具有高K电介质材料的FRAM

    公开(公告)号:US06794705B2

    公开(公告)日:2004-09-21

    申请号:US09751551

    申请日:2000-12-28

    IPC分类号: H01L27108

    摘要: A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive liner (240) and a second conductive liner (242). First conductive layer (240) comprises Pt, and second conductive liner (242) comprises a thin layer of conductive oxide. The multi-layer electrode (246) prevents oxygen diffusion through the top conductive region (244) and reduces material variation during electrode patterning.

    摘要翻译: 一种多层电极(246)及其制造方法,其中通过第一导电衬垫(240)和第二导电衬套(242)将导电区域(244)与阻挡层(222)分离。 第一导电层(240)包括Pt,并且第二导电衬垫(242)包括导电氧化物的薄层。 多层电极(246)防止氧扩散通过顶部导电区域(244)并且减少电极图案化期间的材料变化。

    Self-aligned V0-contact for cell size reduction
    5.
    发明申请
    Self-aligned V0-contact for cell size reduction 失效
    自对准V0接触用于电池尺寸减小

    公开(公告)号:US20060151819A1

    公开(公告)日:2006-07-13

    申请号:US11373080

    申请日:2006-03-09

    IPC分类号: H01L29/94

    CPC分类号: H01L21/76897 H01L28/55

    摘要: An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.

    摘要翻译: FeRAM包括夹在顶电极和底电极之间的铁电材料。 V0触点提供与底层CS触点的电气连接。 使用底部电极对齐V0触点。 衬里层覆盖底部电极的侧壁,并为蚀刻形成V0接触的孔提供停止。 在FeRAM中使用一种形成V0接触的方法,包括。 FeRAM的Fe电容器被封装,蚀刻底部电极,沉积覆盖底部电极的侧壁的衬层,并且蚀刻用于V0接触的孔,直到蚀刻被衬垫层停止。

    MULTI-LAYER BARRIER ALLOWING RECOVERY ANNEAL FOR FERROELECTRIC CAPACITORS
    6.
    发明申请
    MULTI-LAYER BARRIER ALLOWING RECOVERY ANNEAL FOR FERROELECTRIC CAPACITORS 有权
    多层障碍物允许用于电容电容器的恢复电极

    公开(公告)号:US20050013091A1

    公开(公告)日:2005-01-20

    申请号:US10623461

    申请日:2003-07-18

    CPC分类号: H01G4/1245 H01G4/33 H01L28/57

    摘要: A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.

    摘要翻译: 用于铁电电容器的多层屏障包括可渗透氢和氧的扩散阻挡层。 外扩散阻挡层覆盖电容器的铁电体。 在氧退火期间,氧气通过外扩散阻挡层进入铁电体,以便修复在蚀刻期间引起的铁电体损坏。 扩散阻挡层通过在氧退火期间阻挡离开铁电体的分子来减少铁电体的分解。 多层屏障还包括通过氧退火修复铁电体之后沉积在扩散阻挡层上的氢阻挡层。 氢阻挡层允许多层屏障在后端工艺期间阻止氢气进入铁电体。

    Self-aligned V0-contact for cell size reduction
    8.
    发明授权
    Self-aligned V0-contact for cell size reduction 失效
    自对准V0接触用于电池尺寸减小

    公开(公告)号:US07061035B2

    公开(公告)日:2006-06-13

    申请号:US10677852

    申请日:2003-10-01

    IPC分类号: H01L29/94

    CPC分类号: H01L21/76897 H01L28/55

    摘要: An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.

    摘要翻译: FeRAM包括夹在顶电极和底电极之间的铁电材料。 V0触点提供与底层CS触点的电气连接。 使用底部电极对齐V0触点。 衬里层覆盖底部电极的侧壁,并为蚀刻形成V0接触的孔提供停止。 在FeRAM中使用一种形成V0接触的方法,包括。 FeRAM的Fe电容器被封装,蚀刻底部电极,沉积覆盖底部电极的侧壁的衬垫层,并且蚀刻用于VO触点的孔,直到蚀刻被衬垫层停止。

    Multi-layer barrier allowing recovery anneal for ferroelectric capacitors
    10.
    发明授权
    Multi-layer barrier allowing recovery anneal for ferroelectric capacitors 有权
    用于铁电电容器的多层屏障允许恢复退火

    公开(公告)号:US06839220B1

    公开(公告)日:2005-01-04

    申请号:US10623461

    申请日:2003-07-18

    CPC分类号: H01G4/1245 H01G4/33 H01L28/57

    摘要: A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.

    摘要翻译: 用于铁电电容器的多层屏障包括可渗透氢和氧的扩散阻挡层。 外扩散阻挡层覆盖电容器的铁电体。 在氧退火期间,氧气通过外扩散阻挡层进入铁电体,以便修复在蚀刻期间引起的铁电体损坏。 扩散阻挡层通过在氧退火期间阻挡离开铁电体的分子来减少铁电体的分解。 多层屏障还包括通过氧退火修复铁电体之后沉积在扩散阻挡层上的氢阻挡层。 氢阻挡层允许多层屏障在后端工艺期间阻止氢气进入铁电体。