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公开(公告)号：US20050275059A1
公开(公告)日：2005-12-15
申请号：US11145509
申请日：2005-06-03
申请人： Ricardo Mikalo , Christoph Ludwig , Pascal Deconinck , Jan-Malte Schley , Mark Isler , Jens-Uwe Sachse
发明人： Ricardo Mikalo , Christoph Ludwig , Pascal Deconinck , Jan-Malte Schley , Mark Isler , Jens-Uwe Sachse
IPC分类号： H01L21/74 , H01L21/76 , H01L21/763 , H01L29/00
CPC分类号： H01L21/763 , H01L21/743
摘要： Isolation trench arrangement, which isolates adjacent semiconductor structures (1), (2), an isolation trench (3) being formed in such a way that it penetrates from a substrate surface into the substrate volume (0) and has at least one insulating substance (20) and at least one conductive substance (21), and the conductive substance (21) is electrically conductively connected to the substrate (0) via an electrically conductive connection (22).
摘要翻译： 隔离沟槽布置，其隔离相邻的半导体结构（1），（2），隔离沟槽（3），其形成为使得其从衬底表面穿透到衬底体积（0）中并且具有至少一个绝缘物质 （20）和至少一个导电物质（21），并且所述导电物质（21）经由导电连接（22）导电地连接到所述基板（0）。
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公开(公告)号：US20060054964A1
公开(公告)日：2006-03-16
申请号：US10941752
申请日：2004-09-15
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11568
摘要： A semiconductor device comprises a transistor body of boron doped semiconductor substrate and a conterminous isolating area formed of insulating material, wherein an oxy-nitride layer is between the transistor body and the isolating area. This invention can be used in a transistor body for example in an NROM cell.
摘要翻译： 半导体器件包括硼掺杂半导体衬底的晶体管体和由绝缘材料形成的连续隔离区，其中氧化氮化物层位于晶体管本体与隔离区之间。 本发明可用于例如在NROM单元中的晶体管体。
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3.发明申请Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories 有权用于操作电可写和可擦除存储单元的方法和用于电存储器的存储器件公开(公告)号：US20070058443A1
公开(公告)日：2007-03-15
申请号：US11600425
申请日：2006-11-16
申请人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Mikalo
发明人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Mikalo
IPC分类号： G11C16/04
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/26
摘要： A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.
摘要翻译： 提供了一种用于操作电可写和可擦除存储单元的方法，其具有可以在第一和第二方向上操作的通道区域，其中信息被存储为有效参数的差异。
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4.发明申请Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories 有权用于操作电可写和可擦除存储单元的方法和用于电存储器的存储器件公开(公告)号：US20050195650A1
公开(公告)日：2005-09-08
申请号：US11072694
申请日：2005-03-04
申请人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Mikalo
发明人： Joachim Deppe , Mark Isler , Christoph Ludwig , Jens-Uwe Sachse , Jan-Malte Schley , Ricardo Mikalo
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/26 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/26
摘要： A method is provided for operating an electrical writable and erasable memory cell, which has a channel region (2) that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.
摘要翻译： 提供了一种用于操作电可写和可擦除存储单元的方法，其具有可以在第一和第二方向上操作的通道区域（2），其中信息被存储为有效参数的差异。
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公开(公告)号：US20060267078A1
公开(公告)日：2006-11-30
申请号：US11141254
申请日：2005-05-31
申请人： Ricardo Mikalo , Erwin Schroer , Gunther Wein , Jens-Uwe Sachse , Mark Isler , Jan-Malte Schley , Christoph Kleint
发明人： Ricardo Mikalo , Erwin Schroer , Gunther Wein , Jens-Uwe Sachse , Mark Isler , Jan-Malte Schley , Christoph Kleint
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and from a memory layer sequence of dielectric materials that is provided for charge-trapping. The nitride liner is used as an etching stop layer in the formation of sidewall spacers used in a peripheral area to produce source/drain junctions of transistors of the addressing circuitry.
摘要翻译： 氧化区域布置在半导体材料的衬底和氮化物衬垫之间，其覆盖存储单元阵列的字线堆叠和衬底的中间区域，并且被提供以将氮化物衬垫与衬底和存储器层序列分离 的电介质材料，用于电荷捕获。 氮化物衬垫在形成用于外围区域的侧壁间隔物中用作蚀刻停止层，以产生寻址电路的晶体管的源极/漏极结。
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6.发明申请Method for fabricating a semiconductor memory having charge trapping memory cells and semiconductor substrate 失效一种制造具有电荷捕获存储单元和半导体衬底的半导体存储器的方法公开(公告)号：US20050003613A1
公开(公告)日：2005-01-06
申请号：US10856414
申请日：2004-05-27
申请人： Mathias Krause , Christoph Ludwig , Jens-Uwe Sachse , Joachim Deppe , Ralf Richter , Christoph Kleint , Ricardo Mikalo
发明人： Mathias Krause , Christoph Ludwig , Jens-Uwe Sachse , Joachim Deppe , Ralf Richter , Christoph Kleint , Ricardo Mikalo
IPC分类号： H01L21/8246 , H01L27/115 , G11C17/00
CPC分类号： H01L27/11568 , H01L27/115
摘要： Electrically conductive material is introduced into interspaces between the word lines (2) and is partially removed using a mask (6) in such a way that residual portions (7) of the conductive material in each case fill a section of the relevant interspace and produce an electrical contact with source/drain regions (15). With further portions of the conductive material, it is possible to form alignment marks for the fabrication process.
摘要翻译： 导电材料被引入到字线（2）之间的间隙中，并且使用掩模（6）部分地移除，使得导电材料的残留部分（7）在每种情况下都填满相关间隙的一部分并产生 与源/漏区（15）的电接触。 对于导电材料的另外部分，可以形成用于制造工艺的对准标记。
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7.发明授权Method for fabricating a semiconductor memory having charge trapping memory cells and semiconductor substrate 失效一种制造具有电荷捕获存储单元和半导体衬底的半导体存储器的方法公开(公告)号：US07015095B2
公开(公告)日：2006-03-21
申请号：US10856414
申请日：2004-05-27
申请人： Mathias Krause , Christoph Ludwig , Jens-Uwe Sachse , Joachim Deppe , Ralf Richter , Christoph Kleint , Ricardo Mikalo
发明人： Mathias Krause , Christoph Ludwig , Jens-Uwe Sachse , Joachim Deppe , Ralf Richter , Christoph Kleint , Ricardo Mikalo
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： Electrically conductive material is introduced into interspaces between the word lines (2) and is partially removed using a mask (6) in such a way that residual portions (7) of the conductive material in each case fill a section of the relevant interspace and produce an electrical contact with source/drain regions (15). With further portions of the conductive material, it is possible to form alignment marks for the fabrication process.
摘要翻译： 导电材料被引入到字线（2）之间的间隙中，并且使用掩模（6）部分地移除，使得导电材料的残留部分（7）在每种情况下填充相关间隙的一部分并产生 与源/漏区（15）的电接触。 对于导电材料的另外部分，可以形成用于制造工艺的对准标记。
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公开(公告)号：US09556509B2
公开(公告)日：2017-01-31
申请号：US13885593
申请日：2011-11-21
申请人： Ricardo Mikalo , Jens Dienelt
发明人： Ricardo Mikalo , Jens Dienelt
CPC分类号： C23C14/34 , C23C14/3407 , H01J37/3414 , H01J37/3417 , H01J37/3426
摘要： A method, comprising: generating a vapor of a material from a source of said material comprising a plurality of separate solid pieces of said material supported on a surface of a base in a configuration in which said plurality of solid pieces of said target material are arranged at two or more levels to cover the whole of said surface of said base while providing a gap between adjacent pieces at the same level; and depositing said material from said vapor onto a substrate.
摘要翻译： 一种方法，包括：从所述材料的源产生材料的蒸气，所述材料的蒸气包括多个分离的所述材料的固体块，所述多个独立的固体块支撑在基体的表面上，所述构型中所述多个所述目标材料的固体块被布置 在两个或更多个水平上以覆盖所述基座的整个所述表面，同时在相同水平面上的相邻块之间提供间隙; 以及将所述材料从所述蒸气沉积到基底上。
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公开(公告)号：US20100079246A1
公开(公告)日：2010-04-01
申请号：US12241992
申请日：2008-09-30
申请人： Ricardo Mikalo
发明人： Ricardo Mikalo
CPC分类号： H01L27/0676 , H01L21/76883 , H01L23/522 , H01L2924/0002 , H01L2924/12044 , H04Q2213/13095 , H01L2924/00
摘要： An integrated circuit with a rectifier element. One embodiment provides a signal source, an electronic circuit and a rectifier element with a copper layer and a cuprous oxide layer adjacent to and in direct contact with the copper layer. The signal source is configured to drive a signal on a signal output terminal that is electrically coupled to the copper layer. The electronic circuit is electrically coupled to the cuprous oxide layer. The rectifier element may be formed between wiring layers of an integrated circuit.
摘要翻译： 具有整流元件的集成电路。 一个实施例提供了一个信号源，一个电子电路和一个具有铜层和氧化亚铜层的整流元件，它与铜层相邻并且与铜层直接接触。 信号源被配置为驱动电耦合到铜层的信号输出端子上的信号。 电子电路电耦合到氧化亚铜层。 整流元件可以形成在集成电路的布线层之间。
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公开(公告)号：US20130153869A1
公开(公告)日：2013-06-20
申请号：US13701571
申请日：2011-06-03
申请人： Ricardo Mikalo , Anja Wellner , Jens Dienelt , Patrick Too
发明人： Ricardo Mikalo , Anja Wellner , Jens Dienelt , Patrick Too
CPC分类号： H01L51/055 , H01L27/283 , H01L51/0021 , H01L51/0023
摘要： A technique comprising: forming a conductive element of an electronic device on a portion of the surface of a first organic layer, applying a second organic layer over said conductive element and said first organic layer, and then treating at least one of the first and second organic layers to increase the strength of adhesion between said first and second organic layers. Thereby the retention of said conductive element on said first organic layer is improved.
摘要翻译： 一种技术，包括：在第一有机层的表面的一部分上形成电子器件的导电元件，在所述导电元件和所述第一有机层上施加第二有机层，然后处理第一和第二有机层中的至少一个 有机层以增加所述第一和第二有机层之间的粘附强度。 从而改善了所述导电元件在所述第一有机层上的保持。
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