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1.发明授权Amplitude modulator having negative feedback circuit for reducing distortion 失效具有用于减小失真的负反馈电路的幅度调制器
公开(公告)号：US5095290A
公开(公告)日：1992-03-10
申请号：US679450
申请日：1991-04-02
CPC分类号： H03C1/545 , H03C2200/0012 , H03C2200/0025 , H03C2200/0079
摘要： Modulator circuit (MOD) with a modulator proper and a correction signal generator. The modulator proper comprises the cascade connection of an amplifier (T11, T21, CS11, T12, T22, CS12) and a first switching circuit (R11, T31, T51, R12, T32, T52), while the generator comprises the cascade connection of the same amplifier and a second switching circuit (R21, T61, T42, R22, T62, T41) having a correction output (P11, P12) coupled to a feedback input (P21, P22) of the amplifier via a feedback circuit (T71, R31, CS21, T72, R32, CS22). The amplifier and the switching circuits are controlled by a modulating signal and a carrier signal respectively and the first and second switching circuits provide a modulated output signal and a correction signal substantially equal to the envelope of the modulated output signal and used to decrease the modulator distortion.
摘要翻译： 具有调制器的调制器电路（MOD）和校正信号发生器。 调制器适当包括放大器（T11，T21，CS11，T12，T22，CS12）和第一开关电路（R11，T31，T51，R12，T32，T52）的级联连接，而发电机包括级联 具有通过反馈电路（T71，...）耦合到放大器的反馈输入（P21，P22）的校正输出（P11，P12）的相同放大器和第二开关电路（R21，T61，T42，R22，T62，T41） R31，CS21，T72，R32，CS22）。 放大器和开关电路分别由调制信号和载波信号控制，第一和第二开关电路提供基本上等于调制输出信号的包络的调制输出信号和校正信号，并用于减小调制器失真 。
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公开(公告)号：US5262970A
公开(公告)日：1993-11-16
申请号：US760770
申请日：1991-09-16
CPC分类号： H03H17/0607 , H03H17/0621 , H03H17/0664 , H03H2218/06
摘要： A multi-sample multi-channel digital decimator filter producing a Finite Impulse filtering Response (FIR) from 128 digital filter coefficients for 4 independent channels with a decimation ratio of 32, i.e. each from 1,024 kHz 1-bit inputs to 32 kHz multibit outputs, splits cyclically the coefficient values in 16 groups of 8, according to the coefficient positions, into 4 Read Only Memory modules (0, 1, 2, 3). The Read Only Memory modules are coupled to the 4 multipliers (MULT 0, 1, 2, 3), wherein the coefficient value is multiplied by that of the input bit, through a multiplexer (MUXI) being able to cycle through 4 distinct conditions. The 4 adder accumulators (ACC 0, 1, 2, 3) are coupled to the outputs of their respective channel multipliers. They each partially compute in parallel outputs words using one sixteenth of the coefficients and the multiplexer rotates these words, thereby enabling complete computation in 4 cycles. 4 registers (REG 00, 01, 02, 03) are associated to each adder so as to compute 4 staggered output words simultaneously for each channel. A preferred filtering response can reduce the size of the Read Only Memory modules.
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公开(公告)号：US5528636A
公开(公告)日：1996-06-18
申请号：US222672
申请日：1994-04-04
CPC分类号： H04L7/0338 , H04L25/4917 , H04L7/005
摘要： A data, synchronization device adapted to re-synchronize a multi-level digital signal (IN; OUT) with an output or local clock signal (CLKO). In case of a binary signal, the device includes two counter systems (CA1-CC1, MAJ1, SEL1; CA0-CC0, MAJ0, SEL0) each associated with a logical level of the signal and counting the number of successive 1's or 0's respectively. These counter systems produce a count number including the number of counted bits and their level. The device further includes a decoder (DEC) generating in synchronism with the local clock signal (CLKO) a number of bits which is a function of the count numbers. These generated bits constitute the requested output signal (OUT). The data synchronization device further includes delay module (DEL) for deriving from an input clock signal (CLKI) received with the input signal (IN), three intermediate clock signals (OA-OC) shifted in phase with respect to each other and each controlling one of a set of three counters (CA1-CC1; CA0-CC0) included in each of the counter systems. The latter also each include a majority voting module (MAJ1; MAJ0) reading the numbers of bits counted by the three counters of the corresponding set, comparing these numbers and selecting the subset of at least two counters having counted a same number of bits. The number of bits counted by the majority of the set counters is assumed to be correct and is therefore transferred to the decoder (DEC).
摘要翻译： 数据同步装置，其适于使多电平数字信号（IN; OUT）与输出或本地时钟信号（CLKO）重新同步。 在二进制信号的情况下，该装置包括两个计数器系统（CA1-CC1，MAJ1，SEL1; CA0-CC0，MAJ0，SEL0），每个与信号的逻辑电平相关联，并分别对连续1或0的数量进行计数。 这些计数器系统产生包括计数位数及其电平的计数。 该装置还包括与本地时钟信号（CLKO）同步产生一个作为计数号的函数的位数的解码器（DEC）。 这些产生的位构成请求的输出信号（OUT）。 数据同步装置还包括用于从由输入信号（IN）接收的输入时钟信号（CLKI）导出的延迟模块（DEL），相对于彼此同相移位的三个中间时钟信号（OA-OC） 包括在每个计数器系统中的三个计数器（CA1-CC1; CA0-CC0）中的一个。 后者还包括读取由相应组的三个计数器计数的比特数的多数投票模块（MAJ1; MAJ0），比较这些数字并选择计数了相同数量的比特的至少两个计数器的子集。 假设大多数设定计数器计数的位数是正确的，因此被传送到解码器（DEC）。
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4.发明授权Frequency tuning system for tuning a center frequency of an analog bandpass filter 失效用于调谐模拟带通滤波器的中心频率的频率调谐系统
公开(公告)号：US5440264A
公开(公告)日：1995-08-08
申请号：US350705
申请日：1994-12-07
CPC分类号： H03H11/0472 , H03H11/0433
摘要： Based on the insight that the voltage-to-current ratio or gain of a capacitor (Z) at a particular reference frequency is the product of its capacitance value with said reference frequency, a tuning system is disclosed which tunes the center frequency of an analog bandpass filter by tuning the characteristic integrator frequency (fc) of an OTA-C integrator by making the transconductance of the operational transconductance amplifier (OTA) thereof equal to the aforementioned gain at that characteristic frequency. Therefore, the tuning system includes a first tuning path in which the OTA, (or a replica thereof) is included and a second tuning path including another amplifier (B-OTA) "degenerated" by the capacitor (Z) so as to produce the required gain. The gains of both these tuning paths are then equalized by matching means (MM) generating a frequency tuning signal (VTF) which is applied to both OTA and OTA-C.
摘要翻译： 基于以下认识：特定参考频率下的电容器（Z）的电压 - 电流比或增益是其电容值与所述参考频率的乘积，公开了一种调谐模拟器的中心频率的调谐系统 带通滤波器，通过使其运算跨导放大器（OTA）的跨导等于该特征频率处的上述增益来调谐OTA-C积分器的特征积分器频率（fc）。 因此，调谐系统包括其中包括OTA（或其副本）的第一调谐路径和包括由电容器（Z）“退化”的另一个放大器（B-OTA）的第二调谐路径，以便产生 所需增益。 然后，通过产生施加于OTA和OTA-C两者的频率调谐信号（VTF）的匹配装置（MM）来均衡两个这些调谐路径的增益。
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5.发明授权
公开(公告)号：US5625318A
公开(公告)日：1997-04-29
申请号：US541904
申请日：1995-10-10
CPC分类号： H03H11/22
摘要： A tunable quadrature phase shifter including two branches each constituted by the cascade connection of a filter, an amplifier and a summing circuit, and two cross-connections constituted by amplifiers interconnecting the filter of one branch to the summing circuit of the opposite branch. An accurate 90 degrees phase shift between the two output signals is obtained by controlling the tail currents of the four amplifiers. The phase shifter used in mobile telecommunication transceivers may be easily and accurately tuned because the signals used in the summing circuits all have a similar amplitude. It is further adapted to operate with only a 3 Volt battery supply as used in wireless phones. The bandwidth of the amplifiers is increased by using double differential pair amplifiers which behave as cascode arrangements.
摘要翻译： 一个可调谐的正交移相器，包括两个分支，每个分支由滤波器，放大器和求和电路的级联连接构成，以及由一个分支的滤波器将相对分支的求和电路互连的放大器构成的两个交叉连接。 通过控制四个放大器的尾部电流，可以获得两个输出信号之间精确的90度相移。 用于移动电信收发机的移相器可以容易且准确地调谐，因为在求和电路中使用的信号都具有相似的幅度。 它还适用于仅使用无线电话中的3伏电池供电。 通过使用作为共源共栅布置的双差分对放大器来增加放大器的带宽。
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公开(公告)号：US5514950A
公开(公告)日：1996-05-07
申请号：US213594
申请日：1994-03-15
CPC分类号： H03F1/3211 , H03F3/45089 , H03F3/72 , H03F2203/45048 , H03F2203/45311 , H03F2203/45322 , H03F2203/45362 , H03F2203/45466 , H03F2203/45471 , H03F2203/45504
摘要： A differential pair arrangement is disclosed which includes between the poles of a DC supply source the series connection of two parallel first branches and a common second branch. Each first branch includes the series connection of a first impedance Q2, Q3, RL/ Q2', Q3', RL', a main path of a transistor Q1/ Q1'and a second impedance RE/RE', the control electrodes of transistors Q1/ Q1' constituting respective input terminals IN1/ IN2 of the arrangement. The second branch includes a first current source (CCS). The arrangement further includes two third branches between the DC supply source poles, each consisting of the series connection of a second current source ICS/ICS', a respective transistor main path and a resistive impedance means R11, S11, R12, S12/ R11', S11', R12', S12'. These third branches result in an increased DC current through the corresponding transistor, thereby increasing the linearity of the arrangement, whilst the DC current through the first and second impedances does not increase, thereby not increasing the needed supply voltage nor the offset voltage of the arrangement.
摘要翻译： 公开了一种差分对布置，其在直流电源的极之间包括两个平行的第一分支的串联连接和公共第二分支。 每个第一分支包括第一阻抗Q2，Q3，RL / Q2'，Q3'，RL'，晶体管Q1 / Q1'的主路径和第二阻抗RE / RE'的串联连接，晶体管的控制电极 Q1 / Q1'构成各个输入端子IN1 / IN2。 第二分支包括第一电流源（CCS）。 该配置还包括直流电源极之间的两个第三分支，每个分支由第二电流源ICS / ICS'，相应的晶体管主路径和电阻阻抗装置R11，S11，R12，S12 / R11' ，S11'，R12'，S12'。 这些第三分支导致通过相应晶体管的增加的直流电流，从而增加了布置的线性，而通过第一和第二阻抗的直流电流不增加，从而不增加所需电源电压和布置的偏移电压 。
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公开(公告)号：US5191545A
公开(公告)日：1993-03-02
申请号：US759449
申请日：1991-09-13
CPC分类号： H03H17/0223 , H03H17/0621 , H03H17/0657 , H03H2218/06
摘要： A multiplex interpolator handles 4 series of multibit input words . . . , Si, Si+1, . . . applied in parallel at 32 kHz after conversion through an input series to parallel converter (SIPO) and produces 4 series of multibit output words at 256 kHz with the help of a parallel adder/subtractor (ADD) operated in multiplex to compute successively for each of the 4 series of input words, the output words 8Si, 7Si+Si+1, . . . , Si+7Si+1, 8Si+1, . . . , each addition of Si+1-Si being also computed by the adder/subtractor in two steps, first by subtracting (c1) Si from the accumulated (IVC) value and second, by adding (d1) Si+1 to the newly accumulated value, the adder/subtractor being initialized after each pair of steps prior to processing data pertaining to another of the 4 input words in a cyclic manner.
摘要翻译： 多路复用插值器可处理4系列多位输入字。 。 。 ，Si，Si + 1， 。 。 在通过输入序列转换为并行转换器（SIPO）之后，以32kHz并行施加，并且通过在多路复用中并行计算的并行加法器/减法器（ADD）产生256系列的4串多位输出字， 4系列输入字，输出字8Si，7Si + Si + 1，。 。 。 ，Si + 7Si + 1,8Si + 1。 。 。 ，每加一个Si + 1-Si也由加法器/减法器分两步进行计算，首先从积累的（IVC）值中减去（c1）Si，其次通过将（d1）Si + 1加到新累积 值，加法器/减法器在处理与4个输入字中的另一个的数据相关的数据之后，在每对步骤之后被初始化。
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8.发明授权Analog-to-digital converter with cascaded switching control of voltage divider substages 失效具有级联分压器分段开关控制的模数转换器
公开(公告)号：US5563599A
公开(公告)日：1996-10-08
申请号：US72772
申请日：1993-06-03
摘要： The invention concerns an analog to digital converter (ADC1, ADC2) for converting an analog input voltage (Vin) into a digital output voltage (Dout) in at least two stages, (B1, B2, B3, B1', B2', B3'). The reference voltage (Vref) or part thereof driving a stage is applied to that stage via switching means so that the voltage applied to the latter means is determined when the switching means is set, i.e. the latter voltage is not dependent of the setting of the switching means. Two implementations of the converter are described, one (ADC1) which produces the digital signal (Dout) before another analog voltage (Vin) can be processed, and another (ADC2) which allows another analog voltage (Vin) to be processed by a stage after the output of that stage is produced.
摘要翻译： 本发明涉及用于将模拟输入电压（Vin）至少两级（B1，B2，B3，B1'，B2'，B3）转换为数字输出电压（Dout）的模数转换器（ADC1，ADC2） '）。 驱动级的参考电压（Vref）或其一部分经由开关装置施加到该级，使得当开关装置被置位时确定施加到后一装置的电压，即，后一电压不依赖于 开关装置。 描述了转换器的两个实现方式，在另一个模拟电压（Vin）可以处理之前产生数字信号（Dout）的一个（ADC1）和允许另一个模拟电压（Vin）由一个阶段处理的另一个（ADC2） 在该阶段的产出生成之后。
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9.发明授权Data transfer connection between a primary device and a plurality of secondary with a reduced number of links 失效主设备与链路数量减少的多个辅助节点之间的数据传输连接
公开(公告)号：US5263023A
公开(公告)日：1993-11-16
申请号：US699341
申请日：1991-05-13
CPC分类号： H04L12/4135 , H04L12/40
摘要： The primary device (DSP) is connected to m.times.n secondary devices CESLIC1-4) by one data link (10B) comprising the m.times.n data channels assigned to respective secondary devices (ESLIC1-4) say m clock links (GKC0-1) connected to m respective groups each of n secondary devices (ESLIC1-3; ESLIC2-4) and carrying m clock signals having a same clock frequency and being mutually shifted by 1/m.sup.th of a cycle of the clock frequency, and by n read/write links (RD0-1) connected to n respective groups each of m secondary devices (ESLIC1-2; ESLIC3-4) and carrying n read/write signals mutually shifted by one cycle of the clock frequency, each secondary device (ESLIC1-4) belonging to a distinct pair of one group out of the m groups (ESLIC1-3; ESLIC2-4) and of one group out of the n groups (ESLIC1-2; ESLIC3-4).
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公开(公告)号：US4888559A
公开(公告)日：1989-12-19
申请号：US213004
申请日：1988-06-29
CPC分类号： H03F3/303 , H03F1/308 , H03F2200/477
摘要： An amplifier includes two differential amplifiers which are connected to an output stage comprising two field effect transistors of opposite conductivity typed directly coupled in series between opposite poles of a DC voltage source. The junction between the two output transistors constitutes the output of the amplifier. A negative feedback loop connects the amplifier's output to the inputs of the differential amplifiers. A correction arrangement is provided to prevent excessive current consumption and cross-over distortion. Preferably, the correction arrangement uses a pair of current mirror circuits to generate respective measuring currents proportional to the current in each of the output transistors. Each such measuring current is compared with a reference current. Any difference between the measuring current and the reference current causes a change in the voltage on the control electrode of the other output transistor, which in turn results in a change in the output voltage and thus a change in the negative feedback applied to both differential amplifiers.
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