公开(公告)号：US06451669B2

公开(公告)日：2002-09-17

申请号：US09742891

申请日：2000-12-20

申请人： Joaquim Torres ,  Philippe Gayet ,  Michel Haond

发明人： Joaquim Torres ,  Philippe Gayet ,  Michel Haond

IPC分类号： H01L2176

CPC分类号： H01L21/7682 ,  H01L21/31695 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.

摘要翻译： 本发明的一个实施方案涉及一种形成集成电路的金属化水平的方法，包括以下步骤：形成由第一绝缘层横向隔开的金属化水平的金属区域，去除第一绝缘层，非保形地沉积第二绝缘层 绝缘层，使得可以在相邻金属区域之间形成间隙，或者获得多孔层。 第一绝缘层的去除是通过掩模进行的，留下第一绝缘层的保护区域围绕金属区域的部分，以便与穿过第二绝缘层的通孔接触。

公开(公告)号：US06762497B2

公开(公告)日：2004-07-13

申请号：US10046322

申请日：2001-10-23

申请人： Philippe Gayet ,  Eric Granger

发明人： Philippe Gayet ,  Eric Granger

IPC分类号： H01L2348

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating an integrated circuit. According to the method, a second dielectric layer is formed above a first dielectric layer, and holes and/or trenches are etched in the first and second dielectric layers. The holes and/or trenches are filled with metal in order to form electrical connection elements, and at least a third dielectric layer is formed. Holes and/or trenches are selectively etched in the third dielectric layer and the second dielectric layer with respect to the first dielectric layer and the elements, in order to control the depth of the etch. Additionally, there is provided an integrated circuit of the type having metallization levels separated by dielectric layers and metallized vias connecting lines of different metallization levels. The integrated circuit includes first and second metallization levels, first and second superposed dielectric layers located above the first metallization level, and a third dielectric layer located above the first and second dielectric layers. Further, at least one electrical connection element is provided in the third dielectric layer and passes through the second dielectric layer until it comes into contact with the first dielectric layer.

摘要翻译： 一种用于制造集成电路的方法。 根据该方法，在第一电介质层的上方形成第二电介质层，并且在第一和第二电介质层中蚀刻空穴和/或沟槽。 孔和/或沟槽用金属填充以形成电连接元件，并且形成至少第三介电层。 为了控制蚀刻的深度，孔和/或沟槽相对于第一介电层和元件在第三介电层和第二介质层中被选择性蚀刻。 此外，提供了一种具有由电介质层分离的金属化水平和连接不同金属化水平线的金属化通孔的类型的集成电路。 集成电路包括第一和第二金属化层，位于第一金属化层上方的第一和第二叠置电介质层，以及位于第一和第二电介质层上方的第三电介质层。 此外，至少一个电连接元件设置在第三电介质层中并且通过第二电介质层，直到其与第一电介质层接触。

公开(公告)号：US06239025B1

公开(公告)日：2001-05-29

申请号：US08947126

申请日：1997-10-08

申请人： Gordon Bease ,  Philippe Gayet

发明人： Gordon Bease ,  Philippe Gayet

IPC分类号： H01L214763

CPC分类号： H01L21/76804 ,  H01L21/76807 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides an integrated circuit containing at least a portion of a first, horizontal, conductive or semiconductive layer covered by a first electrically insulating layer. A first conductive member is vertically provided through the first electrically insulating layer in electrical contact with the first, horizontal layer. The first conductive member includes a lower, substantially cylindrical portion, and an upper portion comprising an enlarged head. An upper surface of the upper portion is substantially coplanar with an upper surface of the first electrically insulating layer. A second electrically insulating layer is deposited over the upper surface of the upper portion of the first conductive member and the upper surface of the first electrically insulating layer. A second conductive member is provided through the second electrically insulating layer.

摘要翻译： 本发明提供一种集成电路，其包含由第一电绝缘层覆盖的第一，水平，导电或半导体层的至少一部分。 第一导电构件通过第一电绝缘层垂直设置，与第一水平层电接触。 第一导电构件包括下部基本圆柱形部分，以及包括扩大头部的上部。 上部的上表面与第一电绝缘层的上表面基本共面。 第二电绝缘层沉积在第一导电构件的上部的上表面和第一电绝缘层的上表面上。 通过第二电绝缘层提供第二导电构件。

公开(公告)号：US5186786A

公开(公告)日：1993-02-16

申请号：US732192

申请日：1991-07-19

申请人： Jean Galvier ,  Philippe Gayet ,  Annie Tissier

发明人： Jean Galvier ,  Philippe Gayet ,  Annie Tissier

IPC分类号： H01L21/302 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/66 ,  H01L21/768

CPC分类号： B24B37/013 ,  H01J37/32935 ,  H01J37/32963 ,  H01L21/32137 ,  H01L21/76877 ,  H01L22/26 ,  H01J2237/30466 ,  H01J2237/334

摘要： A method for determining the complete elimination of a thin layer (3) deposited on a substrate (1) includes the steps of providing on an area of the substrate (1) an optical diffraction grating (2, 2'), the thin layer deposited on the substrate also covering this diffraction grating, and the etching of the thin layer being also carried out in the area of the diffraction grating; illuminating the grating (2, 2') with a monochromatic light beam; and observing the evolution of the diffracted light during the etching of the thin layer, in order to determine the moment when the material of the thin layer is entirely removed.

摘要翻译： 确定沉积在基板（1）上的薄层（3）的完全消除的方法包括以下步骤：在基板（1）的一个区域上提供光学衍射光栅（2,2'），薄层沉积 在衬底上也覆盖该衍射光栅，并且薄层的蚀刻也在衍射光栅的区域中进行; 用单色光束照射光栅（2,2'）; 并且在蚀刻薄层期间观察衍射光的演变，以便确定薄层的材料被完全去除的时刻。

公开(公告)号：US06525393B1

公开(公告)日：2003-02-25

申请号：US09053405

申请日：1998-04-01

申请人： Philippe Gayet

发明人： Philippe Gayet

IPC分类号： H01L2900

CPC分类号： H01L21/76202

摘要： A method for producing an isolation region on a surface of a semiconductor substrate includes: forming and patterning a masking layer; forming an isolating layer so that a notch exists between an edge of the masking layer and the upper surface of the isolating layer; forming a filling layer over the masking layer and the isolating layer, so that it completely fills the notch; forming field protection spacers adjacent to the masking layer; partially removing the filling layer to expose the upper surface of the isolation layer, the notch remaining filled with a part of the filling layer; and selectively etching the isolating layer from its upper limit until this upper limit is substantially coplanar with the upper surface of the semiconductor substrate. A transistor may be produced in a semiconductor substrate, having a minimum gate length, a minimum width isolation region and wide field isolation region. The isolation regions have substantially coplanar surfaces, also coplanar with an upper surface of the semiconductor substrate. The wide field isolation region has, in an upper surface, a hollow located a distance p from an interface with the upper surface of the semiconductor substrate and the minimum width isolation region has a width less than the sum of the gate length and 2 p.

摘要翻译： 在半导体衬底的表面上制造隔离区域的方法包括：形成和图案化掩模层; 形成隔离层，使得在掩模层的边缘和隔离层的上表面之间存在凹口; 在掩模层和隔离层上形成填充层，使得其完全填充凹口; 形成与掩蔽层相邻的场保护间隔物; 部分地去除填充层以暴露隔离层的上表面，缺口填充有填充层的一部分; 并且选择性地将隔离层从其上限刻蚀，直到该上限基本上与半导体衬底的上表面共面。 可以在具有最小栅极长度，最小宽度隔离区域和宽场隔离区域的半导体衬底中制造晶体管。 隔离区域具有基本上共面的表面，其也与半导体衬底的上表面共面。 宽场隔离区域在上表面中具有位于距离半导体衬底的上表面的界面的距离p的中空，并且最小宽度隔离区域具有小于栅极长度和2p的总和的宽度。

公开(公告)号：US06580130B1

公开(公告)日：2003-06-17

申请号：US09460161

申请日：1999-12-13

申请人： Jean-Pierre Schoellkopf ,  Philippe Gayet

发明人： Jean-Pierre Schoellkopf ,  Philippe Gayet

IPC分类号： H01L2701

CPC分类号： H01L28/20 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated static random access memory device includes four transistors and two resistors defining a memory cell. The four transistors are in a semiconductor substrate and are mutually interconnected by a local interconnect layer. The local interconnect layer is under a first metal level and a portion of the local interconnect layer defines above the substrate a base metal level. The two resistors extend in contact with a portion of the local interconnect layer between the base metal level and the first metal level.

摘要翻译： 集成的静态随机存取存储器件包括限定存储单元的四个晶体管和两个电阻器。 四个晶体管在半导体衬底中并且通过局部互连层相互互连。 局部互连层位于第一金属层之下，并且局部互连层的一部分在基底上限定了基底金属层。 两个电阻器与基底金属层与第一金属层之间的局部互连层的一部分相接触。

公开(公告)号：US5736451A

公开(公告)日：1998-04-07

申请号：US649248

申请日：1996-05-17

申请人： Philippe Gayet

发明人： Philippe Gayet

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76202

摘要： A method for producing an isolation region on a surface of a semiconductor substrate includes: forming and patterning a masking layer; forming an isolating layer so that a notch exists between an edge of the masking layer and the upper surface of the isolating layer; forming a filling layer over the masking layer and the isolating layer, so that it completely fills the notch; forming field protection spacers adjacent to the masking layer; partially removing the filling layer to expose the upper surface of the isolation layer, the notch remaining filled with a part of the filling layer; and selectively etching the isolating layer from its upper limit until this upper limit is substantially coplanar with the upper surface of the semiconductor substrate. A transistor may be produced in a semiconductor substrate, having a minimum gate length, a minimum width isolation region and wide field isolation region. The isolation regions have substantially coplanar surfaces, also coplanar with an upper surface of the semiconductor substrate. The wide field isolation region has, in an upper surface, a hollow located a distance p from an interface with the upper surface of the semiconductor substrate and the minimum width isolation region has a width less than the sum of the gate length and 2p.

摘要翻译： 在半导体衬底的表面上制造隔离区域的方法包括：形成和图案化掩模层; 形成隔离层，使得在掩模层的边缘和隔离层的上表面之间存在凹口; 在掩模层和隔离层上形成填充层，使得其完全填充凹口; 形成与掩蔽层相邻的场保护间隔物; 部分地去除填充层以暴露隔离层的上表面，缺口填充有填充层的一部分; 并且选择性地将隔离层从其上限刻蚀，直到该上限基本上与半导体衬底的上表面共面。 可以在具有最小栅极长度，最小宽度隔离区域和宽场隔离区域的半导体衬底中制造晶体管。 隔离区域具有基本上共面的表面，其也与半导体衬底的上表面共面。 宽场隔离区域在上表面中具有位于距离半导体衬底的上表面的界面距离p的中空，并且最小宽度隔离区域具有小于栅极长度和2p的总和的宽度。

公开(公告)号：US07064053B2

公开(公告)日：2006-06-20

申请号：US10651492

申请日：2003-08-29

申请人： Srdjan Kordic ,  Alain Inard ,  Céline Roussel ,  Philippe Gayet

发明人： Srdjan Kordic ,  Alain Inard ,  Céline Roussel ,  Philippe Gayet

IPC分类号： H01L21/44 ,  H01L21/20 ,  H01L21/311

CPC分类号： H01L28/10 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76819 ,  H01L21/7684 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for fabricating an integrated electrical circuit comprises the formation and then the removal of conducting inserts. Components of the electrical circuit are incorporated into insulating materials superposed on top of a substrate. The process makes it possible to provide an exclusion volume around certain components sensitive to electrostatic coupling, while giving each insulating material a planar surface at the end of a polishing step.

摘要翻译： 一种用于制造集成电路的方法包括形成然后去除导电插入件。 电路的组件被结合到叠加在基板顶部上的绝缘材料中。 该过程使得可以围绕对静电耦合敏感的某些部件提供排除体积，同时在抛光步骤结束时给予每个绝缘材料平面。

公开(公告)号：US06392299B1

公开(公告)日：2002-05-21

申请号：US09449309

申请日：1999-11-24

申请人： Philippe Gayet

发明人： Philippe Gayet

IPC分类号： H01L2348

CPC分类号： H01L23/5222 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect level includes upper and lower partial levels having respective conductive lines offset heightwise from each other. The interconnect level further includes respective dielectric portions separating adjacent conductive lines and extends above and below the conductive lines. At least one descending via connects a conductive line of the upper partial level with a lower element located below the dielectric portions of the interconnect level. The at least one descending via extends through the dielectric portions separating adjacent conductive lines of the lower partial level. At least one ascending via connects a conductive line of the lower partial level with an upper element located above the dielectric portions of the interconnect level. At least one ascending via extends through the dielectric portions separating adjacent conductive lines of the upper partial level.

摘要翻译： 互连电平包括具有彼此高度偏移地偏移的各自导线的上部和下部部分电平。 互连级别还包括分隔相邻导线并且在导线上方和下方延伸的相应电介质部分。 至少一个下降通孔将上部分电平的导线与位于互连电平的电介质部分下方的下部元件连接。 所述至少一个下降通孔延伸穿过分离较低部分电平的相邻导电线的电介质部分。 至少一个上升通孔将下部分电平的导线与位于互连电平的电介质部分上方的上部元件连接。 至少一个上升通孔延伸通过分离上部分电平的相邻导电线的电介质部分。

公开(公告)号：US06355552B1

公开(公告)日：2002-03-12

申请号：US09320201

申请日：1999-05-26

申请人： Philippe Gayet ,  Eric Granger

发明人： Philippe Gayet ,  Eric Granger

IPC分类号： H01L214763

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating an integrated circuit. According to the method, a second dielectric layer is formed above a first dielectric layer, and holes and/or trenches are etched in the first and second dielectric layers. The holes and/or trenches are filled with metal in order to form electrical connection elements, and at least a third dielectric layer is formed. Holes and/or trenches are selectively etched in the third dielectric layer and the second dielectric layer with respect to the first dielectric layer and the elements, in order to control the depth of the etch. Additionally, there is provided an integrated circuit of the type having metallization levels separated by dielectric layers and metallized vias connecting lines of different metallization levels. The integrated circuit includes first and second metallization levels, first and second superposed dielectric layers located above the first metallization level, and a third dielectric layer located above the first and second dielectric layers. Further, at least one electrical connection element is provided in the third dielectric layer and passes through the second dielectric layer until it comes into contact with the first dielectric layer.