Method of forming insulated metal interconnections in integrated circuits
    1.
    发明授权
    Method of forming insulated metal interconnections in integrated circuits 有权
    在集成电路中形成绝缘金属互连的方法

    公开(公告)号:US06451669B2

    公开(公告)日:2002-09-17

    申请号:US09742891

    申请日:2000-12-20

    IPC分类号: H01L2176

    摘要: One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.

    摘要翻译: 本发明的一个实施方案涉及一种形成集成电路的金属化水平的方法,包括以下步骤:形成由第一绝缘层横向隔开的金属化水平的金属区域,去除第一绝缘层,非保形地沉积第二绝缘层 绝缘层,使得可以在相邻金属区域之间形成间隙,或者获得多孔层。 第一绝缘层的去除是通过掩模进行的,留下第一绝缘层的保护区域围绕金属区域的部分,以便与穿过第二绝缘层的通孔接触。

    Heat treatment machine for semiconductors
    2.
    发明授权
    Heat treatment machine for semiconductors 失效
    半导体热处理机

    公开(公告)号:US4581520A

    公开(公告)日:1986-04-08

    申请号:US529108

    申请日:1983-09-02

    CPC分类号: C30B13/24 C30B1/02 C30B1/023

    摘要: A heat treatment machine for heat-treating semiconductor wafers, each wafer having two faces. A first lamp is arranged to heat a first spot of first diameter on one face of the wafer and a second lamp is arranged to heat a second spot of second diameter on the other face of the wafer, both by reflection of emitted light off a focusing reflector. The lamps are moved in tandem such that the first spot travels along an Archimedes spiral relative to the center of the stationary wafer. The centers of the spots coincide, and the second diameter is greater than the first diameter.

    摘要翻译: 一种用于热处理半导体晶片的热处理机,每个晶片具有两个面。 第一灯被布置成加热晶片的一个表面上的第一直径的第一点,并且第二灯被布置成通过发射的光从聚焦的反射来加热晶片的另一个表面上的第二直径的第二点 反射器。 灯串串联移动,使得第一光斑相对于固定晶片的中心沿着阿基米德螺旋行进。 斑点的中心重合,第二直径大于第一直径。

    Integrated semiconductor memory device having quantum well buried in a substrate
    3.
    发明授权
    Integrated semiconductor memory device having quantum well buried in a substrate 有权
    集成半导体存储器件,其量子阱埋在衬底中

    公开(公告)号:US06724660B2

    公开(公告)日:2004-04-20

    申请号:US10022185

    申请日:2001-12-12

    IPC分类号: G11C1604

    摘要: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.

    摘要翻译: 诸如光电子器件和集成半导体存储器件的电子器件包括至少一个集成的存储器点结构,其包括埋在该结构的衬底中并设置在晶体管的绝缘栅极之下的量子阱半导体区域。 偏置电压源适于偏置该结构以使能量子阱或量子阱外的电荷的充电或放电。

    Method of isolating active areas of a semiconductor substrate by shallow
trenches and narrow trenches
    4.
    发明授权
    Method of isolating active areas of a semiconductor substrate by shallow trenches and narrow trenches 失效
    通过浅沟槽和窄沟槽隔离半导体衬底的有源区的方法

    公开(公告)号:US5641704A

    公开(公告)日:1997-06-24

    申请号:US403143

    申请日:1995-03-13

    CPC分类号: H01L21/76205 Y10S148/133

    摘要: The semiconductor device includes in a semiconductor substrate (1) at least one predetermined region (6) of the substrate intended subsequently to form an active area, uncovered on its upper surface and situated between lateral trenches (7) containing an insulative material including a layer (9) of a planarising first oxide and at least one underlying layer (8) of a conformal second oxide. The insulative material can form on either side of said uncovered predetermined region (6) of the substrate a boss (16) on the plane upper surface of the device (D) less than 1000 .ANG. high.

    摘要翻译: 半导体器件包括在半导体衬底(1)中的衬底的至少一个预定区域(6),用于随后形成有源区,未覆盖在其上表面上并且位于包含绝缘材料的横向沟槽(7)之间,所述绝缘材料包括层 (9)和平面化第一氧化物的至少一个下层(8)。 所述绝缘材料可以在所述基板的所述未覆盖的预定区域(6)的任一侧上在所述装置(D)的平面上表面上的小于1000安培高的凸台(16)上形成。

    MOSFET transistor with short channel effect compensated by the gate material
    5.
    发明授权
    MOSFET transistor with short channel effect compensated by the gate material 有权
    具有沟道效应的MOSFET晶体管由栅极材料补偿

    公开(公告)号:US06528399B1

    公开(公告)日:2003-03-04

    申请号:US09606600

    申请日:2000-06-29

    IPC分类号: H01L2122

    CPC分类号: H01L29/4983 H01L21/28105

    摘要: A MOSFET transistor comprising a gate made of silicon-germanium alloy, formed on a single crystal silicon substrate by means of a thin insulating layer, and drain and source regions implanted in the substrate on each side of the gate, characterized in that the gate comprises side regions presenting an increasing germanium percentage towards the sides of the gate facing the drain and source regions. Advantage: compensation of the short channel effect by locally decreasing the work function of the gate material near the drain and source regions.

    摘要翻译: 一种MOSFET晶体管,包括由硅 - 锗合金构成的栅极,其通过薄绝缘层在单晶硅衬底上形成,并且漏极和源极区域注入到栅极的每一侧上的衬底中,其特征在于栅极包括 侧面区域朝着面向漏极和源极区域的栅极的侧面呈现增加的锗百分比。 优点:通过局部降低漏极和源极区附近栅极材料的功函来补偿短沟道效应。

    Process for the production of an oriented monocrystalline silicon film
with localized defects on an insulating support
    6.
    发明授权
    Process for the production of an oriented monocrystalline silicon film with localized defects on an insulating support 失效
    用于在绝缘支撑件上制造具有局部缺陷的取向单晶硅膜的方法

    公开(公告)号:US4773964A

    公开(公告)日:1988-09-27

    申请号:US854385

    申请日:1986-04-21

    申请人: Michel Haond

    发明人: Michel Haond

    CPC分类号: C30B13/34 Y10S117/913

    摘要: This process consists of producing in the insulating support a periodic configuration which, in the form of regularly spaced parallel insulating strips, has overhanging and recessed parts, the width of the overhanging parts being smaller than that of the recessed parts; depositing on the complete structure obtained a silicon film; covering the silicon film with an encapsulating material layer; carrying out heat treatment in order to recrystallize the silicon film in monocrystalline form, said treatment consisting of locally melting the silicon film and displacing the melted zone parallel to the insulating strips, the melted zone being in the form of a line perpendicular to said strips, followed by the elimination of the encapsulating material layer.

    摘要翻译: 该过程包括在绝缘支撑件中产生周期性构造,其以规则间隔的平行绝缘条的形式具有突出和凹陷部分,突出部分的宽度小于凹陷部分的宽度; 在完整结构上沉积获得硅膜; 用封装材料层覆盖硅膜; 进行热处理以使硅膜以单晶形式重结晶,所述处理包括局部熔化硅膜并将熔融区域平行于绝缘条移位,熔融区域为垂直于所述条带的线形式, 然后消除封装材料层。

    Process for the production of an insulating support on an oriented
monocrystalline silicon film with localized defects
    7.
    发明授权
    Process for the production of an insulating support on an oriented monocrystalline silicon film with localized defects 失效
    在具有局部缺陷的取向单晶硅膜上生产绝缘支撑体的方法

    公开(公告)号:US4678538A

    公开(公告)日:1987-07-07

    申请号:US853906

    申请日:1986-04-21

    CPC分类号: C30B13/34

    摘要: Process for the production of an oriented monocrystalline silicon film with localized defects on an insulating support.This process consists of covering a monocrystalline silicon support of orientation (100) with a SiO.sub.2 layer, producing in the latter a configuration having in the form of oriented (100) parallel insulating strips, an alternation of overhanging parts and recessed parts carrying out the etching of the SiO.sub.2 layer in order to locally form at the ends of said layer at least one opening, said etching being continued until the substrate is exposed, depositing on the etched SiO.sub.2 layer a silicon film, covering the silicon film with an encapsulating layer, carrying out a heat treatment of the structure obtained in order to recrystallize the silicon film in monocrystalline form with the same orientation as the substrate and eliminating the encapsulating layer.

    摘要翻译: 用于在绝缘支撑件上制造具有局部缺陷的取向单晶硅膜的方法。 该方法包括用SiO 2层覆盖取向(100)的单晶硅支撑体,后者产生具有取向(100)平行绝缘条形式的构型,突出部分的交替和进行蚀刻的凹陷部分 的SiO 2层,以在所述层的端部局部形成至少一个开口,所述蚀刻继续进行,直到基板被暴露,在蚀刻的SiO 2层上沉积硅膜,用封装层覆盖硅膜,承载 对获得的结构进行热处理,以便以与衬底相同的取向以单晶形式重结晶硅膜并消除封装层。

    Process for fabricating a MOS transistor having two gates, one of which is buried and corresponding transistor
    9.
    发明授权
    Process for fabricating a MOS transistor having two gates, one of which is buried and corresponding transistor 有权
    用于制造具有两个栅极的MOS晶体管的工艺,其中一个栅极被埋入并且对应的晶体管

    公开(公告)号:US06555482B2

    公开(公告)日:2003-04-29

    申请号:US09812717

    申请日:2001-03-20

    IPC分类号: H01L21302

    CPC分类号: H01L29/66772 H01L29/78648

    摘要: A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.

    摘要翻译: 制造MOS晶体管的方法包括在绝缘体上硅衬底内形成第一栅极,形成横向覆盖第一栅极的半导体沟道区,以及在沟道区的每一侧上形成半导体漏极和源极区。 半导体沟道区域和漏极和源极区域可以通过在第一栅极的上表面上外延生长。 通道区域可以通过在通道区域下形成隧道并且用第一电介质至少部分地填充隧道而与第一栅极的上表面隔离。 第二栅极形成在沟道区域上并且横向于沟道区域。 第二栅极可以通过第二电介质与沟道区的上表面分离。

    SOI MOS transistor with a substrate-source connection
    10.
    发明授权
    SOI MOS transistor with a substrate-source connection 失效
    具有基板源连接的SOI MOS晶体管

    公开(公告)号:US5089870A

    公开(公告)日:1992-02-18

    申请号:US534644

    申请日:1990-06-07

    申请人: Michel Haond

    发明人: Michel Haond

    摘要: An SOI MOS transistor comprises at least a highly doped lateral stripe (13, 14) of the same conductivity type as the substrate (3). This stripe extends along the edge of the substrate and of the source region (5) and is shorted with the source region through the conductive source layer (11).

    摘要翻译: SOI MOS晶体管至少包括与衬底(3)相同的导电类型的高度掺杂的横向条纹(13,14)。 该条带沿着基板的边缘和源极区域(5)延伸,并且通过导电源层(11)与源极区域短路。