公开(公告)号：US20090075472A1

公开(公告)日：2009-03-19

申请号：US11857760

申请日：2007-09-19

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US20120329269A1

公开(公告)日：2012-12-27

申请号：US13602119

申请日：2012-09-01

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US08481423B2

公开(公告)日：2013-07-09

申请号：US11857760

申请日：2007-09-19

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

公开(公告)号：US08470706B2

公开(公告)日：2013-06-25

申请号：US13602119

申请日：2012-09-01

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US07749892B2

公开(公告)日：2010-07-06

申请号：US11564358

申请日：2006-11-29

申请人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Son V. Nguyen ,  Alfred Grill ,  Satyanarayana V. Nitta ,  Darryl D. Restaino ,  Terry A. Spooner

发明人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Son V. Nguyen ,  Alfred Grill ,  Satyanarayana V. Nitta ,  Darryl D. Restaino ,  Terry A. Spooner

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76844 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.

摘要翻译： 提供的互连，其包括具有顶表面和下表面的铜导体，其中帽形成在金属导体的顶表面上。 盖由双层叠或多层薄膜形成，层压膜包括超紫（UV）阻挡膜和扩散阻挡膜。 扩散阻挡膜和UV阻挡膜可以通过中间膜分离。

公开(公告)号：US20080122103A1

公开(公告)日：2008-05-29

申请号：US11564358

申请日：2006-11-29

申请人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Son V. Nguyen ,  Alfred Grill ,  Satyanarayana V. Nitta ,  Darryl D. Restaino ,  Terry A. Spooner

发明人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Son V. Nguyen ,  Alfred Grill ,  Satyanarayana V. Nitta ,  Darryl D. Restaino ,  Terry A. Spooner

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76844 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.

摘要翻译： 提供的互连，其包括具有顶表面和下表面的铜导体，其中帽形成在金属导体的顶表面上。 盖由双层叠或多层薄膜形成，层压膜包括超紫（UV）阻挡膜和扩散阻挡膜。 扩散阻挡膜和UV阻挡膜可以通过中间膜分离。

公开(公告)号：US20090224374A1

公开(公告)日：2009-09-10

申请号：US12042873

申请日：2008-03-05

申请人： Ritwik Bhatia ,  Griselda Bonilla ,  Alfred Grill ,  Joshua L. Herman ,  Son Van Nguyen ,  E. Todd Ryan ,  Hosadurga Shobha

发明人： Ritwik Bhatia ,  Griselda Bonilla ,  Alfred Grill ,  Joshua L. Herman ,  Son Van Nguyen ,  E. Todd Ryan ,  Hosadurga Shobha

IPC分类号： H01L23/538 ,  H01L23/58 ,  H01L21/31 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/02348 ,  H01L21/76832

摘要： A dielectric cap, interconnect structure containing the same and related methods are disclosed. The inventive dielectric cap includes a multilayered dielectric material stack wherein at least one layer of the stack has good oxidation resistance, Cu diffusion and/or substantially higher mechanical stability during a post-deposition curing treatment, and including Si—N bonds at the interface of a conductive material such as, for example, Cu. The dielectric cap exhibits a high compressive stress and high modulus and is still remain compressive stress under post-deposition curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.

摘要翻译： 公开了包含相同方法和相关方法的电介质盖，互连结构。 本发明的电介质盖包括多层介电材料堆叠，其中叠层的至少一层在后沉积固化处理期间具有良好的抗氧化性，Cu扩散和/或显着更高的机械稳定性，并且包括Si-N键在 导电材料，例如Cu。 电介质盖表现出高压缩应力和高模量，并且在后沉积固化处理时仍然保持压应力，例如：铜低k后端（BEOL）纳米电子器件，导致较少的膜和器件 开裂和可靠性提高。

公开(公告)号：US07737052B2

公开(公告)日：2010-06-15

申请号：US12042873

申请日：2008-03-05

申请人： Ritwik Bhatia ,  Griselda Bonilla ,  Alfred Grill ,  Joshua L. Herman ,  Son Van Nguyen ,  E. Todd Ryan ,  Hosadurga Shobha

发明人： Ritwik Bhatia ,  Griselda Bonilla ,  Alfred Grill ,  Joshua L. Herman ,  Son Van Nguyen ,  E. Todd Ryan ,  Hosadurga Shobha

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L23/58 ,  H01L23/48

CPC分类号： H01L21/76834 ,  H01L21/02348 ,  H01L21/76832

摘要： A dielectric cap, interconnect structure containing the same and related methods are disclosed. The inventive dielectric cap includes a multilayered dielectric material stack wherein at least one layer of the stack has good oxidation resistance, Cu diffusion and/or substantially higher mechanical stability during a post-deposition curing treatment, and including Si—N bonds at the interface of a conductive material such as, for example, Cu. The dielectric cap exhibits a high compressive stress and high modulus and is still remain compressive stress under post-deposition curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.

摘要翻译： 公开了包含相同方法和相关方法的电介质盖，互连结构。 本发明的电介质盖包括多层介电材料堆叠，其中叠层的至少一层在后沉积固化处理期间具有良好的抗氧化性，Cu扩散和/或显着更高的机械稳定性，并且包括Si-N键在 导电材料，例如Cu。 电介质盖表现出高压缩应力和高模量，并且在后沉积固化处理时仍然保持压应力，例如：铜低k后端（BEOL）纳米电子器件，导致较少的膜和器件 开裂和可靠性提高。

公开(公告)号：US07795740B2

公开(公告)日：2010-09-14

申请号：US12245133

申请日：2008-10-03

申请人： Chih-Chao Yang ,  Griselda Bonilla ,  Qinghuang Lin ,  Terry A. Spooner

发明人： Chih-Chao Yang ,  Griselda Bonilla ,  Qinghuang Lin ,  Terry A. Spooner

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature of the dielectric material such that the treated surfaces become hydrophobic. The treatment step is performed prior to deposition of the noble metal liner and aides in improving the adhesion between the chemically etched dielectric material and the noble metal liner.

摘要翻译： 提供了一种互连结构及其制造方法，其中改善了化学蚀刻的电介质材料和贵金属衬垫之间的粘合性。 根据本发明，对化学蚀刻电介质材料进行改性电介质材料的化学性质使处理后的表面变得疏水的处理步骤。 在沉积贵金属衬垫和助剂以改善化学蚀刻的电介质材料和贵金属衬垫之间的粘附性之前进行处理步骤。

公开(公告)号：US20070273044A1

公开(公告)日：2007-11-29

申请号：US11440984

申请日：2006-05-25

申请人： Chih-Chao Yang ,  Griselda Bonilla ,  Qinghuang Lin ,  Terry A. Spooner

发明人： Chih-Chao Yang ,  Griselda Bonilla ,  Qinghuang Lin ,  Terry A. Spooner

IPC分类号： H01L23/52

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature of the dielectric material such that the treated surfaces become hydrophobic. The treatment step is performed prior to deposition of the noble metal liner and aides in improving the adhesion between the chemically etched dielectric material and the noble metal liner.

摘要翻译： 提供了一种互连结构及其制造方法，其中改善了化学蚀刻的电介质材料和贵金属衬垫之间的粘合性。 根据本发明，对化学蚀刻电介质材料进行改性电介质材料的化学性质使处理后的表面变得疏水的处理步骤。 在沉积贵金属衬垫和助剂以改善化学蚀刻的电介质材料和贵金属衬垫之间的粘附性之前进行处理步骤。